Utilizing Compactflash* On The Intel Ep80579 Integrated Processor Product Line

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Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note John Donovan Technical Marketing Engineer Intel Corporation Muthurajan Jayakumar Technical Marketing Engineer Intel Corporation May 2009 Order Number: 320716-002US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 2 May 2009 Order Number: 320716-002US Contents Contents 1.0 Introduction .............................................................................................................. 7 1.1 Related Documentation ........................................................................................ 7 1.2 References ......................................................................................................... 7 1.3 Acronyms........................................................................................................... 7 2.0 Hardware Overview ................................................................................................... 8 2.1 The Processor ..................................................................................................... 8 2.2 SATA Overview ................................................................................................. 10 2.2.1 SATA Feature List................................................................................... 10 2.3 Local Expansion Bus Overview ............................................................................ 10 2.3.1 Local Expansion Bus Feature List .............................................................. 10 2.4 CompactFlash* ................................................................................................. 11 2.4.1 CF Card Selection ................................................................................... 11 2.4.2 CF Interface Signals ............................................................................... 12 3.0 SATA to CompactFlash* ........................................................................................... 13 3.1 SATA-to-PATA Bridge Solution............................................................................. 13 3.2 SATA to CompactFlash* Adapter ......................................................................... 14 4.0 Local Expansion Bus to CompactFlash*.................................................................... 15 4.1 True IDE Mode Hardware Interface ...................................................................... 15 4.2 Expansion Bus Operation.................................................................................... 17 4.2.1 Outbound Transfers ................................................................................ 18 4.2.2 Chip Select Address Allocation.................................................................. 18 4.2.3 Register Summary.................................................................................. 21 4.2.4 Expansion Bus Interface Configuration ...................................................... 24 4.2.5 Expansion Bus Write/Read Timing Diagrams .............................................. 26 5.0 CompactFlash* Operations ...................................................................................... 28 5.1 Access to the CompactFlash* Registers ................................................................ 28 5.2 Wait for CompactFlash to Get Ready .................................................................... 29 5.3 Switching Expansion Bus Data Width ................................................................... 29 5.4 Read from a Sector............................................................................................ 30 5.5 Write to a Sector ............................................................................................... 30 5.6 Read the Identify Information ............................................................................. 30 Figures 1 2 3 4 5 6 7 8 9 10 Intel® EP80579 Integrated Processor Embedded Block Diagram ....................................... 9 CF Storage Card Block Diagram ................................................................................. 11 SATA to PATA Bridge Diagram ................................................................................... 14 SATA to CF Adapter Diagram ..................................................................................... 15 CompactFlash – True IDE Mode Interface .................................................................... 16 Chip Select Address Allocation When There are no 32-Mbyte Devices Programmed ........... 19 Expansion Bus Memory Sizing.................................................................................... 20 Chip Select Address Allocation when a 32-Mbyte Device is Programmed .......................... 20 Expansion Bus Write (Intel Simplex Mode)................................................................... 27 Expansion Bus Read (Intel, Simplex Mode) .................................................................. 27 May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 3 Contents Tables 1 2 3 4 5 6 7 CF Interface Signal Description...................................................................................12 Register-Table Legend...............................................................................................21 Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration Registers .......................................................................................21 Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through CSRBAR PCI Memory BAR ....................................................22 EXP_TIMING_CS[1-2] - Expansion Bus Timing Registers ................................................23 Timing Extension Parameters Correlation .....................................................................26 True IDE Mode I/O Decoding......................................................................................28 Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 4 May 2009 Order Number: 320716-002US Revision History Revision History Date Revision Description May 2009 002 Updated Section 1.0, “Introduction” Updated Section 2.3, “Local Expansion Bus Overview” Updated Section 4.2, “Expansion Bus Operation” December 2008 001 Initial release May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 5 Revision History Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 6 May 2009 Order Number: 320716-002US 1.0 Introduction 1.0 Introduction This application note describes methods for connecting CompactFlash* (CF) to the Intel® EP80579 Integrated Processor Product Line. The EP80579 is an integrated System On a Chip (SoC) that includes extensive I/O options and provides various storage and bootable operating system options. CompactFlash cards are a viable option in these applications. This document explains the options of connecting CF cards to the Local Expansion Bus or to the SATA port on the EP80579, provides hardware interface details of a CF card configured in ‘True IDE’ mode, and discusses connecting that CF card to the Local Expansion Bus of the EP80579. Connecting CF cards through SATA to PATA bridge devices to the SATA port of the EP80579 is outlined. In addition, the CF architecture and Local Expansion Bus architecture is reviewed. The following sections cover the SATA interface, Local Expansion Bus and CF architecture, Local Expansion Bus initialization/operation, and accessing the CF registers. 1.1 Related Documentation Title Document Number Intel® EP80579 Integrated Processor Product Line Datasheet Using the Intel ® EP80579 Integrated Processor Local Expansion Bus CompactFlash Specification 1.2 320066 321096 (www.compactflash.org) References 1. “CF+ and CompactFlash Specification Revision 4.1”, CompactFlash Association, February 2007. 2. “Microsoft Extensible Firmware Initiative, FAT32 File System Specification, FAT: General Overview of On-Disk Format”, Microsoft Corp., version 1.03, December 6, 2000. 3. “FAT16 Structure Information”, Jack Dobiash, June 17, 1999, http://home.teleport.com/~brainy/fat16.htm. 1.3 Acronyms Acronym ATA CF AT Attachment CompactFlash CFA CompactFlash Association CFI CompactFlash Interface DMA FAT GPIO May 2009 Order Number: 320716-002US Definition Direct Memory Access File Allocation Table General-Purpose Input/Output IDE Integrated Device Electronics IICH Integrated I/O Control Hub Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 7 2.0 Hardware Overview Acronym IMCH LBA Integrated Memory Control Hub Logical Block Addressing LSP Linux Support Package PHY Physical Layer Device PIO Programmed Input/Output PLL Phase Lock Loop SoC System-on-Chip SSP Single Synchronous Serial Port XCVR 2.0 Definition Transceiver Hardware Overview This chapter provides an overview of the Intel® EP80579 Integrated Processor product line architecture. Section 2.1 gives a high-level summary for each of the major blocks and their internal interfaces. Figure 1 shows the major EP80579 blocks. 2.1 The Processor • The EP80579 IA-32 core runs at 600, 1066, and 1200 MHz with an internal 400 or 533 MHz front-side bus (FSB) interface. The IA-32 core features a 256-Kbyte 2-way level 2 cache (L2). • The EP80579 IMCH provides the main path to memory for the IA-32 core and all peripherals that perform coherent I/O (e.g., PCI Express*, the IICH to coherent memory). The IMCH includes the four channel DMA engine as well as a PCI Express* root complex with 1x8, 2x4, or 2x1 interfaces. The memory controller operates at 200-266-333-400 MHz, depending on external DDR and SKU configuration. Depending on SKU, the EP80579 supports a single-channel 64-bit with ECC memory controller for external DDR-2 memory (400, 533, 667, and 800 MHz). For cost-sensitive applications, the EP80579 also supports a 32-bit with ECC mode. • The EP80579 IICH provides a set of PC platform-compatible I/O devices, including two SATA 1.0/2.0 and one USB 1.1/2.0 host controller supporting two USB ports, plus two serial 16550-compatible UART interfaces. The IICH complex interfaces to the MCH through the “NSI” internal bus interface. • The EP80579 Acceleration and I/O Complex (AIOC) supports three Gigabit Ethernet media access controllers, MDIO, Local Expansion Bus, two Controller Area Network (CAN) interfaces, IEEE-1588, and SSP. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 8 May 2009 Order Number: 320716-002US 2.0 Hardware Overview Figure 1. Intel® EP80579 Integrated Processor Embedded Block Diagram Local Expansion Bus MDIO (x1) CAN (x2) SSP (x1) IEEE-1588 (16b @ 80 MHz) GigE MAC GigE MAC GigE MAC #2 #1 #0 Acceleration and I/O Complex IA Complex IMCH (256 KB) L2 Cache IA-32 core Transparent PCI-to-PCI Bridge FSB EDMA Memory Controller Hub IICH APIC, DMA, Timers, Watch Dog Timer, RTC, HPET (x3) PCI Express Interface (x1) SPI LPC1.1 May 2009 Order Number: 320716-002US SATA 2.0 USB 2.0 (x2) (x2) UART (x2) GPIO (x36) SMBus (x2) (Gen1, 1x8, 2x4 or 2x1 root complex) Memory Controller (DDR-2 400/533/667/800, 64b with ECC) Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 9 2.0 Hardware Overview 2.2 SATA Overview The EP80579 contains two SATA ports capable of independent DMA operation. The SATA interface supports data transfer rates up to 1.5 Gb/s or 3.0 Gb/s per port. The SATA host controller contains two modes of operation: a legacy mode using I/O space, and an AHCI mode using memory space. 2.2.1 SATA Feature List • Independent DMA operation on two ports. • Two ports in SATA 1.0a and AHCI mode. • Two ports in AHCI mode only. • Data transfer rates up to 300 Mbyte/s. • Support Gen2m electrical spec (cable not exceeding 2m). 2.3 Local Expansion Bus Overview The Expansion Bus controller provides an interface to external expansion target devices. The Local Expansion Bus interface is provided to allow control and monitoring of external devices. Performance will be significantly lower than “data bus width” and the maximum operating frequency of the EP80579. The Expansion Bus controller includes up to 25-bit address bus and a 16-bit wide data path. The Expansion bus supports Intel multiplexed, Intel non-multiplexed, Intel StrataFlash® technology, Intel StrataFlash® Synchronous Memory, Micron FlowThrough ZBT, Motorola multiplexed, Motorola non-multiplexed, and Texas Instruments Host Port Interface (HPI) target devices. Byte-wide devices may also be used by programming the EXP_TIMING_CS register for 8-bit operation. For TI DSPs that support an internal bus width of 32 bits, the multiplexed HPI-8 or HPI-16 interface can be used to complete these transfers. 2.3.1 Local Expansion Bus Feature List • Outbound transfers (the EP80579 is the master to an external target device). • Eight programmable target chip selects. • Twenty five bits of address; sixteen bits of data. • Supports Intel mode and Motorola mode bus cycles. • Supports Intel StrataFlash® technology. • Supports 66-MHz Intel StrataFlash® Synchronous Memory (16-bit only). • Supports 16-bit Micron Flow-Through ZBT (Zero bus turnaround) SRAMS. • Supports 8-bit and 16-bit Texas Instruments HPI specifications. • Multiplexed or non-multiplexed address / data buses for Intel/Motorola/HPI bus cycles. • Supports even and odd parity generation and calculation for Intel/Motorola/Micron ZBT modes. • Maximum clock input frequency of 80 MHz. • Minimum input clock frequency of 33 MHz. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 10 May 2009 Order Number: 320716-002US 2.0 Hardware Overview 2.4 CompactFlash* CompactFlash has exhibited improvements in reliability, speed, and write cycle tolerance for certain applications. This has made CF an appealing storage option. And there are more advantages that make CF a viable option to replace hard drives: • CompactFlash consumes only a fraction of power in comparison to 2.5" and 3.5" drives (Typical 2.5" and 3.5" hard drives can consume about 10W, while a CompactFlash on average consumes less than 1W of power). • CompactFlash are shock resistant and easily portable with no moving parts, ideal for embedded applications. CompactFlash is a standard specification maintained by the CompactFlash Association (CFA) (www.compactflash.org). The CF Specification describes the connectivity and communications with I/O, storage modules, and compact memory devices. It is widely used in many applications such as portable and desktop computers, digital cameras, handheld data collection scanners, PCS phones, Pocket PCs, PDAs, handy terminals, personal communicators, audio recorders, MP3 players, monitoring devices, and settop boxes. A block diagram of a CF storage card is shown in Figure 2. The controller interfaces with a host system, allowing data to transfer to and from the flash memory module. Figure 2. CF Storage Card Block Diagram D ata In /O u t Host Interface FLA SH M o dule(s) C ontroller C on tro l 2.4.1 CF Card Selection The CF card is a small-form-factor, PCMCIA-compatible, storage and I/O card based on the PCMCIA PC Card ATA specification, and includes a True IDE mode, which is compatible with the ATA/ATAPI-4 standard. CF cards function in three basic interface modes: • True IDE Mode • PC Card I/O Mode • PC Card Memory Mode May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 11 2.0 Hardware Overview For the purposes of this application note, True IDE mode is the basic interface mode of interest and is compatible to the Local Expansion Bus of the EP80579 integrated processor. True IDE – A CF storage card run in True IDE mode that is electrically compatible with an IDE disk drive. A CF storage card is configured in True IDE mode only when the OE# pin (also called ATA SEL#) is grounded by the host during the power-off to power-on cycle. In this mode, the task file registers are also mapped into I/O address space, and the control signals IORD# and IOWR# are used to access I/O locations. Ultra DMA – For SATA application CF cards that support the UDMA Fixed Disk Mode protocol. CF Card Speed – Most CF Cards have reasonable transfer rates of over 30 MB/s for the high speed cards. Card speed is usually specified in "x" ratings, e.g., 133x, 266x, 300x. This is the same system used for CD-ROMs and gives the data rate as a multiple of the data rate of the first audio CD-ROMS. The base rate is 150 kB/s, so for example, 300x = 300 * 150 kB/s = 45 MB/s. CF Card Size – CF Cards are offered in a wide range of storage capacity. For applications targeting alternative solutions to hard drives, CF cards of 4 GB or larger are recommended. 2.4.2 CF Interface Signals Table 1 lists the CF interface signals. Note that the signals listed are for all three common modes of the CF card: PC Card I/O, True IDE and PC Card Memory. Some uncommon control signals, which may not be used in some modes, are also listed. Table 1. CF Interface Signal Description Signal Name Type Description RESET# I Active Low – Reset CF. When the pin is high, this resets the CompactFlash Card. RESET I Active High – Reset CF CS0# (CE1) I Chip Select 0 (Card Select 0) CS1# (CE2) I Chip Select 1 (Card Select 1) A10-A0 I Address Bits [10:0] D15-D0 I/O Data Bits [15:0] INTRQ O Interrupt Request to the Host REG# I Register Select OE#/ATA SEL# I Output Enable/IDE Mode Enable CSEL# I Cable Select IOWR# I I/O Write Strobe IORD# I I/O Read Strobe VS1#, VS2# O Voltage Sense WE# I Write Enable INPACK# O Input. Acknowledge IOIS16#/IOCS16# O 16-Bit Transfer PDIAG# CD1#, CD2# DASP# I/O O I/O Pass Diagnostic Card Detect Drive Active/Slave Present Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 12 May 2009 Order Number: 320716-002US 3.0 SATA to CompactFlash* Table 1. CF Interface Signal Description Signal Name Wait/IORDY 3.0 Type Description O Wait/Ready BVD1 I/O Bus Voltage BVD2 I/O Bus Voltage SPKR I/O Speaker STSCHG# I/O Status Changed RDY/BSY# O Ready/Busy IREG# O Interrupt Request WP O Write Protect VCC 3.3 V Ground (GND) Ground SATA to CompactFlash* Like many other Intel® chipsets with SATA interfaces, the Intel® EP80579 Integrated Processor can seamlessly implement a SATA to CompactFlash solution. Embedded applications in particular tend to have requirements that lean to alternative storage or bootable media other than hard drives. A CF Card as a bootable OS medium is a desirable alternative, which can be implemented via a SATA to PATA bridge device. This section describes some SATA to CF alternatives. There are several devices currently on the market that can provide alternative storage methods to hard drives. This section will focus on the Serial ATA to CompactFlash implementations. The solutions described in this section provide options that include a SATA-to-PATA Bridge integrated into the platform design, or a SATA to CompactFlash reader as a subsystem approach. 3.1 SATA-to-PATA Bridge Solution SATA-to-PATA Bridge devices provide a cost-effective method of creating a SATA to CF card solution on the Intel® EP80579 Integrated Processor. When selecting a SATA-toPATA Bridge, ensure that the device supports ATAPI commands and Ultra DMA. In addition, the bridge chip should support Device bridge functions. A bridge device looks like a SATA device with one side of the device connected to a CF card and other side connected to a SATA interface. Figure 3 shows a block diagram of a design with the SATA-to-PATA Bridge chip. With a minimal amount of discrete components, this bridge device can be interfaced to the EP80579 integrated processor through the SATA interface. The CF card is connected via a 50-pin CompactFlash compatible connector. May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 13 3.0 SATA to CompactFlash* Figure 3. SATA to PATA Bridge Diagram Power: 3.3V, 1.8V power EP80579 SATA Controller SATA PHY SATA to PATA Bridge PATA I/O 50 pin Compact Flash Connector PLL 25 MHz Clock Generator/Crystal/ Oscillator After connecting the EP80579 as shown in Figure 3, the CF Card can be controlled as if it were an ordinary SATA drive, and can be configured as a boot device. 3.2 SATA to CompactFlash* Adapter As a subsystem solution, SATA-to-CF Adapters are another approach to connect CF cards to the SATA interface on the EP80579. Off the shelf accelerated adapters are compatible with most operating systems, and can easily become a bootable device. Most, if not all, of the SATA-to-CF Adapters are subsystems that are designed with a SATA to PATA bridge device. SATA-to-CF adapters are offered with mounting hardware options that enable installation into drive bays or into an enclosure. These adapters typically include SATA data and power cables, but not the CF card. Figure 4 shows a typical SATA-to-CF Adapter, which is simply connected to the EP80579 through the SATA data cable. These adapters also include a CF card slot to interface to the CF card module. Although SATA-to-CF Adapters are typically bootable devices, only certain CF cards are capable of booting. Adapter manufacturers specify that CF cards with UDMA Fixed Disk Mode compatibility are recommended. Depending on design requirements, a 4 GB CF card is typically of sufficient capacity. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 14 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* Figure 4. SATA to CF Adapter Diagram Power: 12V, 5V SATA Data Connector EP80579 SATA Controller SATA to CF Adapter 50 pin CF Slot SATA Power Connector Compact Flash Card A CF card can be either cloned as a hard drive or installed into the SATA-to-CF Adapter. The CF card appears as a SATA drive to any OS and can be configured as a boot device. These SATA-to-CF Adapters are transparent to the operating system and do not require any drivers. 4.0 Local Expansion Bus to CompactFlash* In every embedded application, implementations and requirements differ. Choosing which mode of the CF card to interface to the Expansion bus depends upon product requirements. This application note describes using a CF card in True IDE mode. The Expansion bus supports several protocols, but True IDE mode is compatible to the Intel Simplex protocol (also referred to as Intel non-multiplexed). Therefore the Expansion bus should be configured as Intel Simplex. CF cards supports both 3.3V and 5.0V operation and can interchange between 3.3V and 5.0V systems. Compatible with CF card 3.3V signals, the EP80579 Expansion bus operates at 3.3V I/O; therefore, the interface between the two does not require voltage-shift-level conversion. However, when interfacing a 5.0V CF card, voltage-shiftlevel converters are required. To access a device driver for the Local Expansion Bus that supports connecting and configuring a CF card to the Local Expansion Bus, go to http://download.intel.com/ design/intarch/ep80579/EP80579_CompactFlash.zip. 4.1 True IDE Mode Hardware Interface This section describes the physical and logic interface of the CF card in True IDE mode to the Expansion bus. A CF card is configured in a True IDE mode of operation only when the OE# (ATASEL#) input signal is grounded by the host during the power-up May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 15 4.0 Local Expansion Bus to CompactFlash* sequence. In this mode, the CF card is accessible as if it were an IDE drive operating in PIO mode (non-DMA). Figure 5 shows the interface of the Expansion bus to the CF card in True IDE mode. Interface signal details are covered in the following paragraphs. In True IDE mode, the CF card can simply be interfaced to the EP80579 integrated processor through the Expansion bus by using a 50-pin CompactFlash compatible connector. Note: The interface shown in Figure 5 does not support the IDE DMA mode. The Expansion bus does not have DMA capabilities. The Local Expansion Bus supports eight chip selects to allow up to eight independent external devices to be connected. However, for CompactFlash applications, only two chips selects are required. Any two of the chip selects can be used in a CF application, but EX_CS[1]# and EX_CS[2]# on the EP80579 are referenced in this document. The CF chip select CS0# and CS1# are enabled by two chip select signals (EX_CS[1]# and EX_CS[2]#) from the Expansion bus, and IORD# and IOWR# are controlled by EX_RD# and EX_WR# from the Expansion bus. To meet the timing required by the CF Specification, the chip select is deasserted at least 20 ns after the IORD# or IOWR# is deasserted. Note that in True IDE mode, the CF CS0# is used for the Task File registers, and the chip select CS1# is used for the Device Control registers. In True IDE mode, the CF IOIS16# is asserted low when the CF card is expecting a 16bit data transfer. All Task File operations take place in byte mode using D7-D0, while all data transfers use 16-bit word data. It is not necessary to control this signal; as shown in Figure 5, IOIS16# is not used. The A[2:0] address lines are used to select one of eight registers in the Task File. The usage of the required interface signals (in True IDE mode) are described and shown below. Figure 5. CompactFlash – True IDE Mode Interface Expansion Bus Interface T ru e ID E M o d e In te rfac e E X _ D A T A [1 5 :0 ] E X _ A D D R [2 :0 ] C F D e vic e D [1 5 :0 ] A [2 :0 ] E X _ C S [1 ]# E X _ C S [2 ]# CS0# C S1# EX _R D# IO R D # EX _W R# IO W R # 3 .3 V W E# 3 .3 V S ys te m R e se t In te l® E P 8 0 57 9 In te g ra te d P ro c e s so r p ro d u c t lin e REG # NC NC VS 1# IR E Q # NC NC W A IT # STSCH G# NC NC SPKR# IO IS 1 6 # C D2# C D1# NC NC RESET# OE# A [1 0 :3 ] CSE L# NC WP IN P A C K VS 2# NC NC • A2-A0 – The address lines from the CF card are directly connected to EX_ADDR[2:0] on the Expansion bus. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 16 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* • A10-A3 – The address lines from the CF card are not used and connected to Ground (GND). • D15-D0 – The data lines from the CF card are directly connected EX_DATA[15:0] on the Expansion bus. • CS0 – Chip Select 0 line from the CF card is connected EX_CS[1]# on the Expansion bus. • CS1 – Chip Select 1 line from the CF card is connected EX_CS[2]# on the Expansion bus. • IORD# – The IO Read Strobe line from the CF card is connected to EX_RD# on the Expansion bus. • IOWR# – The IO Write Strobe line from the CF card is connected to EX_WR# on the Expansion bus. • RESET# – The Reset line from the CF card is directly connected to the System Reset circuitry to reset the CF device. • OE# (ATASEL#) – The Output Enable line from the CF card is connected to Ground. To ensure the CF device operates in True IDE mode, this pin must be grounded. • CSEL# – The Card Select line from the CF card is not used and connected to 3.3V. • REG# – The Register Select line from the CF card is not used in True IDE mode and connected to 3.3V through pull-up. • WE# – The Write Enable line from the CF card is not used in True IDE mode and connected to 3.3V through pull-up. • CSEL# - The Card Select line from the CF card is not used and connected to Ground. This signal is used to select Master or Slave drive. In this hardware interface, CSEL# is connected to ground to indicate there is only one drive — the master drive. As discussed, the interface between the CF card and the EP80579 through the Expansion bus in True IDE mode requires no external glue logic. Unused signals and control signals are also shown and designated as “NC” (No Connection). Only power and ground signals are not shown. The RESET# signal is required to directly connect to the System Reset circuitry to reset the CF device at every power-up sequence. 4.2 Expansion Bus Operation The Expansion Bus controller support outbound transfers that are initiated by the EP80579 that targets Expansion Bus slaves. The Expansion data bus is 16 bits wide and the address bus is 25 bits wide. Since the Expansion Bus controller has only one outbound transaction queue, outbound accesses all complete in order. May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 17 4.0 Local Expansion Bus to CompactFlash* 4.2.1 Outbound Transfers For outbound data transfers, the Expansion Bus controller occupies up to 256 Mbytes of address space in the EP80579’s memory map. Eight chip selects are supported to allow up to eight independent external devices to be connected. However, for CompactFlash applications, only two chips selects are required. The signaling characteristics and timing for each chip select is individually programmable. The address space for each chip select is from 512 bytes to 32 Mbytes depending on bits [13:9] (CNFG4_0) of the EXP_TIMING_CS[0:9] registers. Please note that the BIOS for the Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology Development Board sets the Local Expansion Bus LEBSIZE up to 128 Mbytes of MMIO address space. The implication is that if application software sets bit 9 (CNFG4_0) of any of the EXP_TIMING_CS[7-0] registers then only EX_CS[3– 0] are accessible via the IA-32 core. In this mode the IA-32 core will not be able to access any of the EX_CS[6 – 4]. An external clock input, EX_CLK, is required to operate the Expansion interface. The clock frequency can be between 33 MHz and 80 MHz. The frequency selection is dependent on the mode supported by the CF Card. Frequency selection should be determined based on timing performance defined in the CompactFlash Spec Rev 4.1 and the Intel® EP80579 Integrated Processor Product Line Datasheet. 4.2.2 Chip Select Address Allocation The Expansion Bus controller occupies up to 256 Mbytes of address space in the EP80579 memory map. The Expansion Bus controller uses bits 27:0, from the internal bus, to determine how to translate the internal bus address to the Expansion Bus address. If there are no 32-Mbyte devices programmed (i.e., all eight EXP_TIMING_CS registers bit 9 equal 0), the lower 24 bits of the internal bus address are translated to the lower 24 bits of the Expansion Bus address, EX_ADDR [23:0]. EX_ADDR[24] will always be zero. Bits 26:24 of the internal bus are used to decode one of eight chip select regions implemented by the Expansion bus, each region being 16 Mbytes. Address bit 27 is not used and will currently alias each chip select region as shown on the left side of Figure 6. The address of the MMBAR registers may vary (are not at a fixed address). Please read the PCI Configuration registers to find the MMBAR registers. MMBAR should be read via the PCI Configuration register located in Bus number M, Device number 8, Function number 0 at offset 0x14h as noted in Table 3. CSRBAR should also be read via the same PCI Configuration register mentioned in the last paragraph. CSRBAR is at offset 0x10h. MMBAR is used as a base for the Address Allocation shown in Figure 6 and Figure 8. CSRBAR is used to access and program the Local Expansion Bus timing control registers and EXP_CNFG0 -Configuration Register 0. If all of the EXP_TIMING_CS[0-7] (CSRBAR + 0 through 0x1C) LEB_SIZE [13:9] are less than or equal to 16 Mbytes, the MMBAR chip select addresses are 16 Mbytes. Therefore: CS0 is accessed when the EP80579 integrated processor reads/writes from (MMBAR + 0) to (MMBAR + 0x1000000 – 1). CS1 is accessed when the EP80579 integrated processor reads/writes from (MMBAR + 0x1000000) to (MMBAR + 0x2000000 – 1) Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 18 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* CS2 is accessed when the EP80579 integrated processor reads/writes from (MMBAR + 0x2000000) to (MMBAR + 0x3000000 – 1) Please note that, by default, all of the EXP_TIMING_CS[0-7] are less than or equal to 16 Mbytes in size, and the Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology Development Board BIOS programs the MMBAR size to request 128 Mbytes of MMIO space for MMBAR which could be 4 or 8 chip selects depending on whether it is a 16 or 32 Mbyte device. Figure 6. Chip Select Address Allocation When There are no 32-Mbyte Devices Programmed cs_n[7] (alias) 128 Mbytes CNFG[4:0] = 0b11110 SIZE = 16 Mbytes MMBAR + 0xFFFFFFF MMBAR + 0xF000000 ... ... cs_n[0] (alias) cs_n[7] cs_n[6] MMBAR + 0x8000000 0b11100 : 8 Mbytes MMBAR + 0x7000000 MMBAR + 0x6000000 cs_n[5] MMBAR + 0x5000000 128 Mbytes cs_n[4] MMBAR + 0x4000000 cs_n[3] MMBAR + 0x3000000 cs_n[2] 0b11010 : 4 Mbytes MMBAR + 0x2000000 cs_n[1] 0b11000 : 2 Mbytes MMBAR + 0x1000000 16 MB 0b10110 : 1 Mbytes 0b00000 : 512 Bytes cs_n[0] MMBAR + 0x0000000 cs_n[x] The right side of Figure 6 shows the implementation of bit 13:10 of the each Timing and Control (EXP_TIMING_CS) register. A Timing and Control (EXP_TIMING_CS) register is implemented for each of the eight chip selects. Each chip select defines a base region size of 512 bytes with the actual size of the region provided by the formula shown in Figure 7. If the address is outside of the programmed region, the Expansion Bus controller responds with an error. May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 19 4.0 Local Expansion Bus to CompactFlash* Figure 7. Expansion Bus Memory Sizing Region Size = 2(9+CNFG[4:1] + 16*CNFG[0]) For Examples of how to use this feature: If bits 13:9 of Timing and Control (EXP_TIMING_CS0) Register 0 = “00000” an address space of 29 = 512 Bytes is defined for chip select 0 (EX_CS0_N). If bits 13:9 of Timing and Control (EXP_TIMING_CS1) Register 1 = “10000” an address space of 217 = 128KBytes is defined for chip select 1 (EX_CS[1]#EX_CS[2]#). If bits 13:9 of Timing and Control (EXP_TIMING_CS2) Register 2 = “11110” an address space of 224 = 16Mbytes is defined for chip select 2 (EX_CS[2]#). If bits 13:9 of Timing and Control (EXP_TIMING_CS7) Register 7 = “00001” an address space of 225 = 32Mbytes is defined for chip select 7 (EX_CS7_N). If there is a 32-Mbyte device programmed in any of the eight EXP_CS_TIMING registers, a different memory map is used (as shown in Figure 8). The lower 25 bits of the internal bus address are translated to the lower 25 bits of the Expansion Bus address, EX_ADDR [24:0]. Bits 27:25 of the internal bus are used to decode one of eight chip-select regions implemented by the Expansion bus, each region being 32 Mbyte. If a design has 16-Mbyte or smaller devices on all of the chip selects, one of the EXP_CS_TIMING registers could be programmed to a 32-Mbyte device so the Expansion Bus address mapping will not change if that design switches to a 32-Mbyte device sometime in the future. The Expansion Bus controller will still work with the smaller device, but an error response will not be generated if there is an access outside the device window for that device. Figure 8. Chip Select Address Allocation when a 32-Mbyte Device is Programmed CNFG[4:0] = 0b00001 SIZE = 32 Mbytes 0b11110 : 16 Mbytes cs_n[7] MMBAR + 0xFFFFFFF MMBAR + 0xE000000 cs_n[6] MMBAR + 0xC000000 0b11100 : 8 Mbytes cs_n[5] 256 Mbytes MMBAR + 0xA000000 cs_n[4] MMBAR + 0x8000000 cs_n[3] cs_n[2] MMBAR + 0x6000000 0b11010 : 4 Mbytes MMBAR + 0x4000000 cs_n[1] 0b11000 : 2 Mbytes MMBAR + 0x2000000 32 MB 0b10110 : 1 Mbytes 0b00000 : 512 Bytes cs_n[0] MMBAR + 0x0000000 Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 20 cs_n[x] May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* 4.2.3 Register Summary Accesses to Expansion Bus registers (CSBAR) are only via 32-bit transfers. Accesses other than 32-bit result in unpredictable operation. Accesses to all reserved bits must be written with zero unless otherwise specified. All reserved address spaces must not be read. All writes to reserved address spaces result in unpredictable operation. The Local Expansion Bus registers materialize in the PCI space. Table 2. Register-Table Legend Attribute Legend RV Reserved RO Read Only RW Read/Write WO Write Only RS Set automatically when read RC Cleared automatically when read WC Write to clear. See individual bit description for more details The Expansion bus is controlled and configured by ten registers: eight timing and control registers, and two configuration registers. For this application note, only two control registers, and one configuration/status register, are referenced. 4.2.3.1 Local Expansion Bus Interface: Bus M, Device 8, Function 0: The Local Expansion Bus interface includes the registers listed in Table 3, and Table 4. These registers materialize in PCI configuration and MMIO (via PCI BAR) spaces. The details of these registers can be found in the Intel® EP80579 Integrated Processor Product Line Datasheet. Table 3. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h Offset 00h: VID: Vendor Identification Register 8086h 02h 03h Offset 02h: DID: Device Identification Register 503Dh 04h 05h Offset 04h: PCICMD: Device Command Register 0000h 06h 07h Offset 06h: PCISTS: PCI Device Status Register 0010h 08h 08h Offset 08h: RID: Revision ID Register Variable 09h 0Bh Offset 09h: CC: Class Code Register 068000h 0Eh 0Eh Offset 0Eh: HDR: Header Type Register 10h 13h Offset 10h: CSRBAR: Control and Status Registers Base Address Register 00000000h 14h 17h Offset 14h: MMBAR: Expansion Bus Base Address Register 00000000h 2Ch 2Dh Offset 2Ch: SVID: Subsystem Vendor ID Register 0000h 2Eh 2Fh Offset 2Eh: SID: Subsystem ID Register 0000h 34h 34h Offset 34h: CP: Capabilities Pointer Register DCh 00h 3Ch 3Ch Offset 3Ch: IRQL: Interrupt Line Register 00h 3Dh 3Dh Offset 3Dh: IRQP: Interrupt Pin Register 01h 40h 43h Offset 40h: LEBCTL: LEB Control Register 00h May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 21 4.0 Local Expansion Bus to CompactFlash* Table 3. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value DCh DCh Offset DCh: PCID: Power Management Capability ID Register DDh DDh Offset DDh: PCP: Power Management Next Capability Pointer Register DEh DFh Offset DEh: PMCAP: Power Management Capability Register 0023h E0h E1h Offset E0h: PMCS: Power Management Control and Status Register 0000h E4h E4h Offset E4h: SCID: Signal Target Capability ID Register 01h E4h 09h E5h E5h Offset E5h: SCP: Signal Target Next Capability Pointer Register F0h E6h E6h Offset E6h: SBC: Signal Target Byte Count Register 09h E7h E7h Offset E7h: STYP: Signal Target Capability Type Register 01h E8h E8h Offset E8h: SMIA: Signal Target IA Mask Register 00h E9h E9h Offset E9h: SMME: Signal Target ME Mask Register EAh EBh Offset EAh: SDATA: Signal Target Data Register 00h ECh ECh Offset ECh: SINT: Signal Target Raw Interrupt Register 00h F0h F0h Offset F0h: MCID: Message Signalled Interrupt Capability ID Register 05h F1h F1h Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register F2h F3h Offset F2h: MCTL: Message Signalled Interrupt Control Register F4h F7h Offset F4h: MADR: Message Signalled Interrupt Address Register F8h F9h Offset F8h: MDATA: Message Signalled Interrupt Data Register 0000h 00h 0000h 00000000h 0000h . Table 4. Offset Start Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through CSRBAR PCI Memory BAR Offset End Register ID - Description Default Value 00000004h 00000007h "EXP_TIMING_CS[1] - Expansion Bus Timing Register on" page 22 00000000h 00000008h 0000000B "EXP_TIMING_CS[2] - Expansion Bus Timing Register on" page 23 00000000h 4.2.3.2 Timing and Control Registers 4.2.3.2.1 EXP_TIMING_CS[1-2] - Expansion Bus Timing Registers The Local Expansion Bus supports eight chip selects to allow up to eight independent external devices to be connected. However, for CompactFlash applications, only two chips selects are required. Any two of the chip selects can be used in a CF application, but CS1 and CS2 on the EP80579 are referenced in this document. There are eight registers — called the Timing and Control (EXP_TIMING_CS) registers — that define the operating mode for each chip select. In this application note, it is assumed that the CF card is connected in True IDE mode to the Expansion bus, as shown in Figure 5. For CompactFlash applications, only two chips selects are required. Any two of the chip selects can be used in a CF application, but CS1 and CS2 are referenced in this document. Therefore, the CF chips selects are connected to Expansion Bus Chip Select 1 and 2. Hence, for CompactFlash functionality, two registers, out of these eight registers, each having timing information for CS1 and CS2 respectively need to be programmed. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 22 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* The details of how to configure these registers for CF card applications is defined above Section 4.2.4, “Expansion Bus Interface Configuration”. The EXP_TIMING_CS registers may only be written if there is not an outstanding Expansion Bus transaction. Software must ensure that all outstanding Expansion Bus transfers are complete before changing the EXP_TIMING_CS registers. Table 5. EXP_TIMING_CS[1-2] - Expansion Bus Timing Registers (Sheet 1 of 2) Description: Timing and Control Registers View: PCI Size: 32 bit Bit Range 31 30 BAR: CSRBAR Bus:Device:Function: M:8:0 Default: 00000000h Bit Acronym 00000004h Offset Start: at 4h Offset End: 0000000Bh at 4h Power Well: Core Bit Description Sticky Bit Reset Value Bit Access CSx_EN 0 = Chip Select x disabled 1 = Chip Select x enabled 0h RW PAR_EN 0 = Parity is not generated or compared 1 = Parity is generated and compared Parity is only supported for Intel, Motorola, and Micron ZBT modes. 0h RW 29 : 28 T1 – Address timing T1_ADDR_TM 00 = Generate normal address phase timing 01 - 11 = Extend address phase by 1 - 3 clocks 0h RW 27 :26 T2 – Setup / Chip Select Timing T2_SU_CS_TM 00 = Generate normal setup phase timing 01 - 11 = Extend setup phase by 1 - 3 clocks 0h RW 25 : 22 T3_STRB_TM T3 – Strobe Timing 0000 = Generate normal strobe phase timing 0001-1111 = Extend strobe phase by 1 - 15 clocks 0h RW 21 : 20 T4_HOLD_TM T4 – Hold Timing 00 = Generate normal hold phase timing 01 - 11 = Extend hold phase by 1 - 3 clocks 0h RW 19 : 16 T5 – Recovery Timing T5_RCVRY_TM 0000 = Generate normal recovery phase timing 0001-1111 = Extend recovery phase by 1 - 15 clocks 0h RW CYC_TYPE 00 = Configures the Expansion Bus for Intel cycles. 01 = Configures the Expansion Bus for Motorola cycles. 10 = Configures the Expansion Bus for HPI cycles. (HPI reserved for chip selects [7:4] only) 11 = Configures the Expansion Bus for Micron ZBT cycles 0h RW CNFG_4_0 Device Configuration Size. Calculated using the formula: SIZE OF ADDR SPACE = 2(9+CNFG[4:1]+16*CNFG[0]) For Example: 00000 = Address space of 29 = 512 Bytes 00010 = Address space of 210 = 1024 Bytes … 10000 = Address space of 217 = 128 Kbytes … 11100 = Address space of 223 = 8 Mbytes 11110 = Address space of 224 = 16 Mbytes 00001 = Address space of 225 = 32Mbytes 0h RW 15 :14 13 : 09 May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 23 4.0 Local Expansion Bus to CompactFlash* Table 5. EXP_TIMING_CS[1-2] - Expansion Bus Timing Registers (Sheet 2 of 2) Description: Timing and Control Registers View: PCI Size: 32 bit BAR: CSRBAR 00000004h Offset Start: at 4h Offset End: 0000000Bh at 4h Bus:Device:Function: M:8:0 Default: 00000000h Power Well: Core Bit Reset Value Bit Access Sync_Intel Synchronous Intel StrataFlash® select. This bit must be 0 if CYC_TYPE is not programmed to Intel cycles. 0 = Target device is not a Synchronous Intel StrataFlash 1 = Target device is a Synchronous Intel StrataFlash 0h RW 07 EXP_CHIP 0 = Target device is not a EP80579 1 = Target device is a EP80579. This bit must only be set to 1 when CYC_TYPE is configured to be Intel Cycles and Sync_Intel is set to 0. 0h RW 06 BYTE_RD16 Byte read access to Half Word device 0 = Byte access disabled. 1 = Byte access enabled. 0h RW 05 HRDY_POL HPI HRDY polarity (reserved for exp_cs_n[7:4] only) 0 = Polarity low true. 1 = Polarity high true. 0h RW 04 MUX_EN 0 = Separate address and data buses. 1 = Multiplexed address / data on data bus. 0h RW 03 SPLT_EN 0 = Internal Bus split transfers disabled. 1 = Internal Bus split transfers enabled. 0h RW 02 Reserved Reserved. This bit must be written with a ‘0’. Writing a ‘1’ will result in unpredictable behavior. 0h RW 01 WR_EN 0 = Writes to CS region are disabled. 1 = Writes to CS region are enabled. 0h RW 00 BYTE_EN 0 = Expansion bus uses 16-bit-wide data bus 1 = Expansion bus uses only 8-bit data bus 0h RW Bit Range Bit Acronym Bit Description 08 4.2.4 Sticky Expansion Bus Interface Configuration There are eight registers called the Timing and Control (EXP_TIMING_CS) registers that define the operating mode for each chip select. In this application note, it is assumed that the CF card is connected in True IDE mode to the Expansion bus as shown in Figure 5. Therefore, the CF chip selects are connected to Expansion Bus Chip Select 1 and 2. Note: To access a device driver for the Local Expansion Bus that supports connecting and configuring a CF card to the Local Expansion Bus, go to http://download.intel.com/ design/intarch/ep80579/EP80579_CompactFlash.zip. Chip Select 1 and 2 can be configured to operate with devices that require an Intel, Synchronous Intel, Micron ZBT or Motorola microprocessor-style bus accesses. These chip selects can be configured to operate in a multiplexed or a simplex mode of operation for either Intel- or Motorola-style bus accesses. As described earlier, the Cycle Type for CF card applications must set to Intel type, which is configured by bits Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 24 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* 15, 14, and 8 of each Timing and Control (EXP_TIMING_CS) register. Table 5 and Table 6 shows the possible settings for the Cycle Type selection using bits 15, 14, and 8 of the Timing and Control (EXP_TIMING_CS) register. Once the Intel Cycle Type is configured, the mode of operation must be set. There are two configurable modes of operation for each chip select: multiplexed and nonmultiplexed. For CF card applications, non-multiplexed mode must be set. Bit 4 of the Timing and Control (EXP_TIMING_CS) register is used to select this mode. If bit 4 of the Timing and Control (EXP_TIMING_CS) register is cleared to logic 0, the access mode for that chip select is non-multiplexed. The size of the data bus for each device connected to the Expansion bus must be configured. The data bus size is selected on a per-chip-select basis, allowing the most flexibility when connecting devices to the Expansion bus. There are two valid selections that can be configured for each data bus size, 8-bit or 16-bit. Bit 0 of each Timing and Control (EXP_TIMING_CS) register is used to select the data bus size on a per-chipselect basis. Each chip select can be independently enabled or disabled by setting a value in bit 31 of each Timing and Control (EXP_TIMING_CS) register. Clearing bit 31 of the Timing and Control (EXP_TIMING_CS) register to logic 0 disables the corresponding chip select. Setting bit 31 of the Timing and Control (EXP_TIMING_CS) register to logic 1 enables the corresponding chip select. Accesses to chip selects that are disabled result in an error response. Each chip select region has the ability to be write-protected by setting bit 1 of each Timing and Control (EXP_TIMING_CS) register. When bit 1 of Timing and Control (EXP_TIMING_CS) register is cleared to logic 0, writes to a specified chip select region results in an error response. When bit 1 of Timing and Control (EXP_TIMING_CS) register is set to logic 1, writes are allowed to a specified chip select region. Chip Select 0 will be write-protected after reset. One final set of parameters that may be set prior to using Expansion Bus Interface Chip Select 1 and 2. After boot up, these parameters may be adjusted for Chip Select 0 as well. These five parameters are the timing extension parameters for each phase of an Expansion Bus access. There are five phases to every Expansion Bus access: • T1 – Address Timing • T2 – Setup/Chip Select Timing • T3 – Strobe Timing • T4 – Hold Timing • T5 – Recovery Phase The Expansion-bus address is used to present the 25 bits of the address [24:0] used for the Expansion bus access accompanied by an address latch enable output signal, EX_ALE, for multiplexed devices. The address phase normally lasts two clock cycles in multiplexed mode. The address phase may be extended by one to three clock cycles using the T1 - Address Timing parameter, bits 29:28, in the Timing and Control (EXP_TIMING_CS) register for the particular chip select. When the address phase T1 is extended, the ALE pulse is extended and always deasserts one cycle prior to the end of the T1 phase. The lower address bits are placed onto the data bus (i.e., for a 16-bit data bus, EX_DATA contains EX_ADDR[15:0]) along with EX_ADDR[24:0] signals during the first cycle of the address phase. During the second cycle of the address phase, the data bus now will output data when attempting to complete a write or tristate when attempting to complete a read. The address signals will retain their state. May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 25 4.0 Local Expansion Bus to CompactFlash* The chip-select signal is presented for one Expansion bus phase before the Strobe Phase. The chip select will be presented for the remainder of the Expansion bus cycles (setup, strobe, and hold phases). The Setup/Chip Select Timing phase may also be extended by one to three clock cycles, using bits 27:26 of the Timing and Control (EXP_TIMING_CS) register, T2 – Setup/Chip Select Timing parameter. The Strobe Phase of an Expansion-bus access is when the read or write strobe is applied. The 25 Expansion Bus Interface Address bits are maintained in nonmultiplexed mode or the Expansion Bus Interface Data bus is switched from address to data when configured in multiplexed mode during the Strobe Phase. The Strobe Phase may be extended from one to 15 clock cycles, as defined by programming bits 25:22 of the Timing and Control (EXP_TIMING_CS) register, T3 – Strobe Timing parameter. The Hold Phase of an Expansion-bus access is provided to allow a hold time for data to remain valid after the data strobe has transitioned to an invalid state. During a write access, the Hold Phase provides hold time for data written to an external device on the Expansion bus, after the strobe pulse has completed. During a read access, the Hold Phase allows an external device time to release the bus after driving data back to the controller. The Hold Phase may be extended one to three clock cycles, using bits 21:20 of the Timing and Control (EXP_TIMING_CS) register, T4 – Hold Timing parameter. After the address and chip select is de-asserted, the Expansion bus controller can be programmed to wait a number of clocks before starting the next Expansion bus access. This action is referred to as the Recovery Phase. The Recovery Phase is may be extended one to 15 clock cycles using bits 19:16 of the Timing and Control (EXP_TIMING_CS) register, T5 – Recovery Timing parameter. 4.2.5 Expansion Bus Write/Read Timing Diagrams The Expansion bus supports several different cycle types, but as described earlier, CF applications must use the Simplex Intel Cycle type. This section includes write and read timing diagrams for the Intel Simplex Mode. When referring to the following timing diagrams it should be noted that the timing extension parameters defined in the CompactFlash Specification Revision 4.1 correlate to those of on the EP80579, as defined in Table 6. Table 6. Timing Extension Parameters Correlation CompactFlash Specification Table 22 EP80579 N/A T1 Address timing - Always program to 0 t1 T2 Setup/Chip Select Timing - Calculated from EX_CLK and PIO Mode t2 T3 Strobe Timing - Calculated from EX_CLK and PIO Mode. Some modes have different timing for register read/write and data transfer. Max t4, t6 T4 Hold Timing - Same as t4/t6 in CF Specification T5 Recovery Phase Timing - Command inactive time delay before sending another command. t2i Description Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 26 May 2009 Order Number: 320716-002US 4.0 Local Expansion Bus to CompactFlash* 4.2.5.1 Intel Simplex Mode Write Access Note: When referring to the CompactFlash Specification- All waveforms are shown with the asserted state high. Negative true signals appear inverted on the bus relative to the diagrams. Figure 9. Expansion Bus Write (Intel Simplex Mode) T3 T4 T5 T1 T2 (1-4 Cycles) (1-4 Cycles) (1-16 Cycles) (1-4 Cycles) (1-16 Cycles) EX_CLK EX_CS_N EX_ADDR EX_WR_N output data EX_DATA 4.2.5.2 Intel Simplex Mode Read Access Figure 10. Expansion Bus Read (Intel, Simplex Mode) T3 T4 T5 T1 T2 (1-4 Cycles) (1-4 Cycles) (1-16 Cycles) (1-4 Cycles) (1-16 Cycles) EX_CLK EX_CS_N EX_ADDR valid address EX_RD_N EX_DATA May 2009 Order Number: 320716-002US input data Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 27 5.0 CompactFlash* Operations 5.0 CompactFlash* Operations CompactFlash operations from software programming guidelines are described in this section. 5.1 Access to the CompactFlash* Registers Control and access to the CF card in True IDE mode is done through a set of registers, the so-called CF-ATA registers or ‘task file’: Table 7. True IDE Mode I/O Decoding -CS1 -CS0 A2 A1 A0 -IORD=0 -IOWR=0 Note 1 0 0 0 0 RD Data WR Data 8 or 16 bit 1 0 0 0 1 Error Register Features 8 bit 1 0 0 1 0 Sector Count Sector Count 8 bit 1 0 0 1 1 Sector No Sector No 8 bit 1 0 1 0 0 Cylinder Low Cylinder Low 8 bit 1 0 1 0 1 Cylinder High Cylinder High 8 bit 1 0 1 1 0 Select Card/Head Select Card/Head 8 bit 1 0 1 1 1 Status Command 8 bit 0 1 1 1 0 Alt Status Device Control 8 bit These registers are addressed by three address lines and two chip select lines: A0, A1, A2, CS0, and CS1. To get access to these registers, a 8-bit value is used as offset. The two most significant bits of the offsets are used to distinguish Chip Select 1 or 2, and the four least significant bits are address offsets of the registers. Based on Table 7, these registers are denoted as follows: #define CF_DATA 0x20 #define CF_ERROR 0x21 #define CF_SECT_CNT 0x22 #define CF_SECT_NUM 0x23 #define CF_CYL_L 0x24 #define CF_CYL_H 0x25 #define CF_DRV_HEAD 0x26 #define CF_STATUS 0x27 #define CF_FEATURES 0x21 #define CF_COMMAND 0x27 All the above registers [registers that have addresses such as “0x2y”] are accessed via the address MMBAR+ 0x01000000h with y as an offset. Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 28 May 2009 Order Number: 320716-002US 5.0 CompactFlash* Operations For example, CF_DATA read/write is accessed via an address of MMBAR+0x01000000+0x0. The following table provides CF register addresses. Register Address CF_DATA MMBAR+0x01000000+0x0 CF_ERROR MMBAR+0x01000000+0x01 CF_SECT_CNT MMBAR+0x01000000+0x02 CF_SECT_NUM MMBAR+0x01000000+0x03 CF_CYL_L MMBAR+0x01000000+0x04 CF_CYL_H MMBAR+0x01000000+0x05 CF_DRV_HEAD MMBAR+0x01000000+0x06 CF_STATUS MMBAR+0x01000000+0x07 CF_FEATURES MMBAR+0x01000000+0x01 CF_COMMAND MMBAR+0x01000000+0x07 #define CF_ALTSTATUS 0x16 #define CF_DEV_CTR 0x16 Both the CF_ALTSTATUS and CF_DEV_CTR registers [registers that have addresses such as “0x1z”] can be accessed via the address MMBAR+ 0x02000000h with z as an offset. CF_ALTSTATUS and CF_DEV_CTR are accessed via an address of MMBAR+0x02000000+0x6. The following table provides the addresses of these registers. Register Address CF_ALTSTATUS MMBAR+0x02000000+0x6 CF_DEV_CTR MMBAR+0x02000000+0x6 Please note that CF_ALTSTATUS is a read register and CF_DEV_CTR is a write register, and both are located at same address. 5.2 Wait for CompactFlash to Get Ready Before any command is issued to the CF card, the card needs to be checked for readiness. The CF_STATUS register provides this status information. When the CF card is ready, the ready bit (bit 6 of the CF_STATUS register) must be 1, and the Busy bit (bit 7 of the CF_STATUS register) must be zero. 5.3 Switching Expansion Bus Data Width In True IDE mode all CF registers are 8 bits wide and reside on byte-aligned addresses except for the CF_DATA register, which is 16 bits wide. The CF_DATA register is used by the host to read/write the CF data buffer. In order to read/write from the CF_DATA register, the Expansion bus must be configured to produce 16-bit-wide data access. In order to read/write the other CF internal register, the Expansion bus must be configured to produce 8-bit-wide data access. Hence, depending on which CF registers are being accessed, it is necessary to switch the Expansion bus data width. May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 29 5.0 CompactFlash* Operations Before the Expansion bus data width is switched, the code must ensure the last Expansion bus transaction has completed. This is done by reading a CF internal register then using the returned value to force the host to stall until the data is returned. 5.4 Read from a Sector Once a read command is issued by the host, the CF card fills the internal data buffer inside the CF with one sector worth of data. The host then repeatedly reads the CF_DATA register to retrieve that sector worth of data from the CF internal data buffer. When reading from CF, logical block addressing (LBA) is used. The next sequence of steps show how this is set up. • The LBA is written to the following registers: — Sector number: CF_SECT_NUM = LBA7~0 — Cylinder Low: CF_CYL_L = LBA15~8 — Cylinder High: CF_CYL_H = LBA23~16 — Head: CF_DRV_HEAD(LSB3~0) = LBA27~24 • The sector count register CF_SECT_CNT is loaded with a value to indicate how many sectors to read. • A read sectors command 0x20 is written to the command register CF_COMMAND to start the reading process: • The CF card will put a sector of data in the internal buffer, and then set the DRQ bit and clear the BSY bit in the CF_STATUS register. • The host then can read the data from the internal buffer by repeatedly reading the CF_DATA register. 5.5 Write to a Sector In write operation, the host (after issuing a write sector command to the CF card) repeatedly writes to the CF_DATA register. Once the CF card’s internal buffer is filled, the buffer’s content is then written to a sector. Steps to write to a sector are similar to those in Section 5.4 except that (after setting up all the other registers) a write sector command 0x30 is written to the CF_COMMAND register. After this command is issued, the CF card will indicate it is ready by setting the DRQ bit and clearing the BSY bit in the CF_STATUS register. The host then can repeatedly write data to the internal buffer When finishing writing the data, the Expansion bus is switched back to 8-bit width after issuing a read instruction to CF_STATUS register to make sure the Expansion Bus write operation is completed. 5.6 Read the Identify Information When a value 0xEC is written to the CF_COMMAND register of the CF card, the internal buffer of the CF card is filled with 512 bytes of information, including the signature of the CF card, the default number of heads, cylinders, sectors per track, capability, as well as other parameters. §§ Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 30 May 2009 Order Number: 320716-002US 5.0 CompactFlash* Operations May 2009 Order Number: 320716-002US Utilizing CompactFlash* on the Intel® EP80579 Integrated Processor Product Line Application Note 31