Vias Of Analog Design Dr. P. Subbanna Bhat

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Enabling Knowledge Leaders Vias of Analog Design Dr. P. Subbanna Bhat Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 1 Enabling Knowledge Leaders Agenda • Growth trends of Microelectronics • Digital and Analog • Current Trends Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 2 Enabling Knowledge Leaders History. . . Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 3 Enabling Knowledge Leaders Electronic Numerical Integrator And Computer • ENIAC (1943-46)  ENIAC (1943-46) • 17,468 vacuum tubes o 24m x 2.6m x 0.9m • 7,200 crystal diodes o 27,000 Kg • 1500 relays o 150 KW • 70,000 resistors o 100 KHz clock • 10,000 capacitors o 0.2 ms (basic m/c cycle) • 5 million soldered joints o 2.8 ms (10 digit x 10 digit) Dell Laptop 2.53 GHz, 4 GB RAM, 450 GB HD, 66 W, 2.2 Kg Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 4 Enabling Knowledge Leaders Growth trends . . . • Supply voltage – 300V. . .12V . . 5V. . . – 3.3V . . . 2.4V . . . 1.8V . . . 1.2V . . . • Power consumption – Watts. . . mW. . . µW . . . • Speed – 3 MHz . . . 3 GHz . . . • Size – Vacuum tubes, BJT, MOS, . . . – 350nm . .. 180nm. . . 90 nm. . . 45 nm . . . Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 5 Enabling Knowledge Leaders Engg. Issues. . . • Reliability, Repeatability, functionality, cost, ergonomics, maintenance . . . • Speed, complexity Component density, efficiency (functional, power) . . . • Hierarchy, Modularity, Regularity, Locality, fabrication . . . • Self improvement loop . . . Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 6 Enabling Knowledge Leaders Digital & Analog Domains Digital : 95% – Computation, Storage Analog & Mixed Signal: 5% – – – – ADC, DAC Voltage & Current References Voltage regulators (LDO, Buck, Boost . . .) Multiplier, PLL, FLL , . . . Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 7 Enabling Knowledge Leaders Signal Processing System Power Management Physical world Analog Filter ADC Digital DAC Analog Filter Physical world Clock Voltage/Current Reference Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 8 Enabling Knowledge Leaders Vias of Analog Design MOSFET Device Current Mirror Cascode Amplifier Differential Amplifier OPAMP & Comparator Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 9 Enabling Knowledge Leaders MOSFET Device • Multiple roles – Capacitor, Resistor, Diode, Switch, Amplifier • Voltage controlled device – Negligible loading • Easy paralleling – No current hogging • Small size – Higher packing density • Ease of fabrication – Fewer layers on Silicon • Unipolar device – Less Noisy Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 10 Enabling Knowledge Leaders Current Mirror • Q-point stability • Current reference • Active load (Stable, high gain amplifier) • Linear Current Amplifier Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 11 Enabling Knowledge Leaders Current mirror (4) ekLakshya VLSI Labs © Copyright: Dr. P Subbanna Bhat Aug 03, 12 Enabling Knowledge Leaders Cascode Amplifier • Basic Configurations : CS, CG, CD • Cascode : CS-CG • Cascode: High Gain, High Bandwidth • Cascode: High input and output impedance Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 13 Enabling Knowledge Leaders Three Basic Configurations © Copyright: Dr. P Subbanna Bhat Enabling Knowledge Leaders Cascode Amplifier © Copyright: Dr. P Subbanna Bhat Enabling Knowledge Leaders Operational Amplifier • Differential Amplifier with Large gain.  High CMRR - Rejects common mode noise  High CMRR - Ignores DC bias variations • Used with (dominant) negative feedback  Inversion property  Improved linearity  Reduced output offset Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 16 Enabling Knowledge Leaders Two stage OPAMP IT 2 IT 2 IT Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 17 Enabling Knowledge Leaders Analog & Mixed Mode Domain • Signal integrity – Filters – Noise and RF related Issues • Power Management – LDO – Buck, Boost • ADC – DAC – Flash, SAR, Dual Slope – Pipeline ADC – Oversampling (Sigma delta) ADC • Input /Output Ports Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 18 Enabling Knowledge Leaders VLSI : Levels of Activity • (Software . . .) • Artificial Intelligence (Neural Network, Fuzzy . . .) • Algorithms – Architecture (DSP . . . ) • Architecture (Von Neumann, Harvard . . .CISC, RISC) • Circuit domain (Analog, Digital , Mixed . . .) • Device Technology (BJT, MOS . . .) • VLSI Technology (180 nm, 90 nm, 45 nm . . .) • Materials Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 19 Enabling Knowledge Leaders VLSI : Design Issues • • • • • • • • • • Signal Integrity Speed Power management Silicon Area CAD Automation – Physical Design Technology Computation – Algorithms Architecture Packaging Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 20 Enabling Knowledge Leaders Artificial Intelligence (1) • Digital computer is based on binary logic • Humans think a little differently ! • Can we build computers that ‘think’ like the humans ? Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 21 Enabling Knowledge Leaders Artificial Intelligence (2) Binary Logic System Human Mind – Processes data  Identifies Patterns – Location addressability  Content Addressability – Rote process  Learns from Experience – Logical reasoning  Approximate reasoning Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 22 Enabling Knowledge Leaders Thank You Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 23 Enabling Knowledge Leaders Vias of Analog Design © Copyright: Dr. P Subbanna Bhat 24 Enabling Knowledge Leaders Amplifier Configurations CS stage : High gain* , Moderate Bandwidth CD stage : Unity gain , High Bandwidth CG stage : High gain*, High Bandwidth * Requires large load impedance ekLakshya VLSI Labs © Copyright: Dr. P Subbanna Bhat Aug 03, 25 Enabling Knowledge Leaders CS Amplifier AV 11  AV 22 AV ,mid   g m rds || RD  © Copyright: Dr. P Subbanna Bhat