Transcript
FEATURES
PIN CONFIGURATION AD8420
Maximum supply current: 90 μA Minimum CMRR: 100 dB Drives heavy capacitive loads: ~700 pF Rail-to-rail output Input voltage range goes below ground Gain set with 2 external resistors Can achieve low gain drift at any gain Very wide power supply range Single supply: 2.7 V to 36 V Dual supply: ±2.7 V to ±18 V Bandwidth (G = 100): 2.5 kHz Input voltage noise: 55 nV/√Hz High dc precision Maximum offset voltage: 125 μV Maximum offset drift: 1 μV/°C Maximum differential input voltage: ±1 V 8-lead MSOP package
NC
8
VOUT
+IN 2
+
–
7
FB
–IN
3
–
+
6
REF
–VS
4
5
+VS
1
TOP VIEW (Not to Scale)
09945-001
Data Sheet
Wide Supply Range, Micropower, Rail-to-Rail Instrumentation Amplifier AD8420
Figure 1.
Table 1. Instrumentation Amplifiers by Category1 General Purpose AD8221, AD8222 AD8220, AD8224 AD8226, AD8227 AD8228
APPLICATIONS
AD8295, AD8224
Bridge amplifiers Pressure measurement Medical instrumentation Portable data acquisition Multichannel systems
1
Zero Drift AD8231 AD8290 AD8293G80, AD8293G160 AD8553 AD8556 AD8557
Military Grade AD620 AD621 AD524 AD526 AD624
Low Power AD8420 AD8235 AD8236 AD627 AD8226 AD8227 AD623 AD8223
Digital Gain AD8250 AD8251 AD8253 AD8231
See www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION The AD8420 is a low cost, micropower, wide supply range, instrumentation amplifier with a rail-to-rail output and a novel architecture that allows for extremely flexible design. It is optimized to amplify small differential voltages in the presence of large common-mode signals. The AD8420 is based on an indirect current feedback architecture that gives it an excellent input common-mode range. Unlike conventional instrumentation amplifiers, the AD8420 can easily amplify signals at or even slightly below ground without requiring dual supplies. The AD8420 has rail-to-rail output, and the output voltage swing is completely independent of the input commonmode voltage.
Rev. A
Single-supply operation, micropower current consumption, and rail-to-rail output swing make the AD8420 ideal for batterypowered applications. Its rail-to-rail output stage maximizes dynamic range when operating from low supply voltages. Dualsupply operation (±15 V) and low power consumption make the AD8420 ideal for a wide variety of applications in medical or industrial instrumentation. The AD8420 is available in an 8-lead MSOP package. Performance is specified over the full temperature range of −40°C to +85°C, and the device is operational from −40°C to +125°C.
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AD8420
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Gain Accuracy ............................................................................ 20
Applications ....................................................................................... 1
Input Voltage Range ................................................................... 20
Pin Configuration ............................................................................. 1
Input Protection ......................................................................... 20
General Description ......................................................................... 1
Layout .......................................................................................... 21
Revision History ............................................................................... 2
Driving the Reference Pin ......................................................... 21
Specifications..................................................................................... 3
Input Bias Current Return Path ............................................... 22
Absolute Maximum Ratings............................................................ 7
Radio Frequency Interference (RFI) ........................................ 22
Thermal Resistance ...................................................................... 7
Output Buffering ........................................................................ 23
ESD Caution .................................................................................. 7
Applications Information .............................................................. 24
Pin Configuration and Function Descriptions ............................. 8
AD8420 in Electrocardiography (ECG) .................................. 24
Typical Performance Characteristics ............................................. 9
Classic Bridge Circuit ................................................................ 25
Theory of Operation ...................................................................... 19
4 mA to 20 mA Single-Supply Receiver .................................. 25
Architecture................................................................................. 19
Outline Dimensions ....................................................................... 26
Setting the Gain .......................................................................... 19
Ordering Guide .......................................................................... 26
REVISION HISTORY 1/15—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Specifications Section .................................................. 3 Changes to Quiescent Current Parameter, Table 2 ...................... 4 Changes to Common-Mode Rejection Ratio (CMRR) Parameter, Table 3 and Quiescent Current Parameter, Table 3......... 5 Changes to ESD Parameter, Table 4 ............................................... 7 Changes to Figure 9, Figure 11, Figure 13, and Figure 14 ......... 10 Changes to Figure 15, Figure 16 Caption, Figure 18 Caption, and Figure 20 Caption.................................................................... 11 Changes to Figure 38 ...................................................................... 14 Change to Figure 40 Caption ........................................................ 15 Changes to Figure 56 Caption....................................................... 17 Changes to Figure 57 Caption....................................................... 18 Changes to Figure 58 and Architecture Section ......................... 19 Changes to Gain Accuracy Section .............................................. 20 Changes to Driving the Reference Pin Section........................... 21 Changes to Output Buffering Section .......................................... 23 Changes to 4 mA to 20 mA Single-Supply Receiver Section .... 25 3/12—Revision 0: Initial Version
Rev. A | Page 2 of 26
Data Sheet
AD8420
SPECIFICATIONS +VS = +5 V, −VS = 0 V, VREF = 0.5 V, V+IN = 0.5 V, V−IN = 0.5 V, TA = 25°C, G = 1 to 1000, RL = 20 kΩ, specifications referred to input, unless otherwise noted. All Table 2 limits are valid from VS = 3 V to VS = ±5 V, unless otherwise specified. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz CMRR at 1 kHz NOISE Voltage Noise Spectral Density Peak to Peak Current Noise Spectral Density Peak to Peak VOLTAGE OFFSET Offset Average Temperature Coefficient Offset RTI vs. Supply (PSR) INPUTS Input Bias Current1
Average Temperature Coefficient Input Offset Current
Average Temperature Coefficient Input Impedance Differential Common Mode Differential Input Operating Voltage Input Operating Voltage (+IN, −IN, REF, or FB)
DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 Slew Rate
Test Conditions/Comments VCM = 0 V to 2.7 V
Min
Typ
Max
100 100
Unit dB dB
f = 1 kHz, VDIFF ≤ 100 mV f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV
55 1.5
nV/√Hz μV p-p
f = 1 kHz f = 0.1 Hz to 10 Hz
80 3
fA/√Hz pA p-p
VS = 3 V to VS = 5 V VS = ±5 V TA = −40°C to +85°C VS = 2.7 V to 5 V Valid for REF and FB pair, as well as +IN and −IN TA = +25°C TA = +85°C TA = −40°C TA = −40°C to +85°C TA = +25°C TA = +85°C TA = −40°C TA = −40°C to +85°C
125 150 1
μV μV μV/°C dB
27 24 30
nA nA nA pA/°C nA nA nA pA/°C
86
20
30 1 1 1 0.5 130||2 1000||2
TA = –40°C to +85°C TA = +25°C TA = +85°C TA = –40°C
VS = ±5 V −1 V to +1 V output step −4.5 V to +4.5 V output step −4.5 V to +4.5 V output step
Rev. A | Page 3 of 26
−1 −VS − 0.15 −VS − 0.05 −VS − 0.2
+1 +VS − 2.2 +VS − 1.8 +VS − 2.7
MΩ||pF MΩ||pF V V V V
250 25 2.5 0.25
kHz kHz kHz kHz
3 130 1 1
μs μs ms V/μs
AD8420 Parameter GAIN2 Gain Range Gain Error G=1 G = 10 to 1000 Gain vs. Temperature OUTPUT Output Swing
Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current
Data Sheet Test Conditions/Comments G = 1 + (R2/R1)
Min
Typ
1 VOUT = 0.1 V to 1.1 V, VREF = 0.1 V VOUT = 0.2 V to 4.8 V TA = −40°C to +85°C VS = 5 V, RL = 10 kΩ to midsupply VS = ±5 V, RL = 20 kΩ to ground TA = +25°C TA = +85°C TA = −40°C
0.05
−VS + 0.1 −VS + 0.1 −VS + 0.1
Max
Unit
1000
V/V
0.02 0.1 10
% % ppm/°C
+VS − 0.15 +VS − 0.2 +VS − 0.15
V V V mA
36
V
90 110 75
μA μA μA
+85 +125
°C °C
10 Single-supply operation3 VS = 5 V TA = +25°C TA = +85°C TA = −40°C
TEMPERATURE RANGE Specified Operational4
2.7 55
−40 −40
1
70
The input stage uses PNP transistors; therefore, input bias current always flows out of the device. For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current. Minimum supply voltage indicated for V+IN, V−IN, and VREF = 0 V. 4 See the Typical Performance Characteristics section for operation between 85°C and 125°C. 2 3
Rev. A | Page 4 of 26
Data Sheet
AD8420
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1 to 1000, RL = 20 kΩ, specifications referred to input, unless otherwise noted. Table 3. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz CMRR at 1 kHz NOISE Voltage Noise Spectral Density Peak to Peak Current Noise Spectral Density Peak to Peak VOLTAGE OFFSET Offset Average Temperature Coefficient Offset RTI vs. Supply (PSR) INPUTS Input Bias Current2
Average Temperature Coefficient Input Offset Current
Average Temperature Coefficient Input Impedance Differential Common Mode Differential Input Operating Voltage Input Operating Voltage (+IN, −IN, REF, or FB)
DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 Slew Rate GAIN3 Gain Range Gain Error G=1 G = 10 to 1000 Gain vs. Temperature
Test Conditions/Comments VCM = −10 V to +10 V
Min
Typ
Max
92 92
Unit dB dB
f = 1 kHz, VDIFF ≤ 100 mV f = 0.1 Hz to 10 Hz, VDIFF ≤ 100 mV
55 1.5
nV/√Hz μV p-p
f = 1 kHz f = 0.1 Hz to 10 Hz
80 3
fA/√Hz pA p-p
VS = ±15 V1 TA = −40°C to +85°C VS = ±15 V Valid for REF and FB pair, as well as +IN and −IN TA = +25°C TA = +85°C TA = −40°C TA = −40°C to +85°C TA = +25°C TA = +85°C TA = −40°C TA = −40°C to +85°C
250 1
μV μV/°C dB
27 24 30
nA nA nA pA/°C nA nA nA pA/°C
100
20
30 1 1 1 0.5 130||3 1000||3
TA = −40°C to +85°C TA = +25°C TA = +85°C TA = −40°C
−1 −VS − 0.15 −VS − 0.05 −VS − 0.2
−1 V to +1 V output step −5 V to +5 V output step −5 V to +5 V output step
1 +VS − 2.2 +VS − 1.8 +VS − 2.7
MΩ||pF MΩ||pF V V V V
250 25 2.5 0.25
kHz kHz kHz kHz
3 130 1 1
μs μs ms V/μs
G = 1 + (R2/R1) 1 VOUT = ±1 V VOUT = ±10 V TA = −40°C to +85°C
Rev. A | Page 5 of 26
0.05
1000
V/V
0.02 0.1 10
% % ppm/°C
AD8420 Parameter OUTPUT Output Swing RL = 20 kΩ to Ground
Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current
Data Sheet Test Conditions/Comments
Min
TA = +25°C TA = +85°C TA = –40°C
−VS + 0.13 −VS + 0.15 −VS + 0.11
Typ
Max
Unit
+VS − 0.2 +VS − 0.23 +VS − 0.16
V V V mA
±18
V
120 145 110
μA μA μA
+85 +125
°C °C
10 Dual-supply operation4 VS = ±15 V TA = +25°C TA = +85°C TA = −40°C
TEMPERATURE RANGE Specified Operational5
±2.7 70
−40 −40
1
85
See the Typical Performance Characteristics section for the offset voltage vs. supply. The input stage uses PNP transistors; therefore, input bias current always flows out of the device. 3 For G > 1, errors from External Resistor R1 and External Resistor R2 should be considered in addition to these specifications, including error from FB pin bias current. 4 Minimum positive supply voltage indicated for V+IN, V−IN, and VREF = 0 V. With V+IN, V−IN, and VREF = −VS, minimum supply is ±1.35 V. 5 See the Typical Performance Characteristics section for operation between 85°C and 125°C. 2
Rev. A | Page 6 of 26
Data Sheet
AD8420
ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE
Table 4. Parameter Supply Voltage Output Short-Circuit Current Maximum Voltage at −IN or +IN Minimum Voltage at −IN or +IN Maximum Voltage at REF or FB Minimum Voltage at REF or FB Storage Temperature Range ESD Human Body Model Charge Device Model Machine Model
θJA is specified for a device in free air.
Rating ±18 V Indefinite −VS + 40 V −VS − 0.5 V +VS + 0.5 V −VS − 0.5 V −65°C to +150°C
Table 5. Package 8-Lead MSOP, 4-Layer JEDEC Board
ESD CAUTION
4 kV 1.25 kV 0.2 kV
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Rev. A | Page 7 of 26
θJA 135
Unit °C/W
AD8420
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8
VOUT
+IN 2
NC 1 +
–
7
FB
–IN 3
–
+
6
REF
5
+VS
–VS 4
TOP VIEW (Not to Scale)
09945-002
AD8420
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions Pin No. 1
Mnemonic NC
2 3 4 5 6 7 8
+IN −IN −VS +VS REF FB VOUT
Description This pin is not connected internally. For best CMRR vs. frequency and leakage performance, connect this pin to negative supply. Positive Input. Negative Input. Negative Supply. Positive Supply. Reference Input. Feedback Input. Output.
Rev. A | Page 8 of 26
Data Sheet
AD8420
TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, +VS = 5 V, RL = 20 kΩ, unless otherwise noted. 700 MEAN: 4.63764 SD: 1.09498
MEAN: –34.8195 SD: 31.3406
600
NUMBER OF HITS
500 400 300
500 400 300
200
200
100
100
0 –150
–100
–50
0
50
100
150
VOS (µV)
0
09945-003
NUMBER OF HITS
600
0
2
4
6
8
10
CMRR, ±15V (µV/V)
Figure 3. Typical Distribution of Input Offset Voltage
09945-008
700
Figure 6. Typical Distribution of CMRR 700 MEAN: 22.706 SD: 0.615728
MEAN: 22.6643 700 SD: 0.6058
600
400 300
500 400 300
200
200
100
100
0 20
21
22
23
24
25
POSITIVE BIAS CURRENT (nA)
0 20
22
23
24
25
gm2 POSITIVE BIAS CURRENT (nA)
Figure 7. Typical Distribution of REF, FB Bias Current
Figure 4. Typical Distribution of Input Bias Current
1200 MEAN: 0.00144205 SD: 0.112088
1000
1000
NUMBER OF HITS
1200 MEAN: 0.000646761 SD: 0.111551
800
600
400
800
600
400
0 –0.9
–0.6
–0.3
0
0.3
0.6
OFFSET CURRENT (nA)
0.9
0 –0.9
–0.6
–0.3
0
0.3
0.6
gm2 OFFSET CURRENT (nA)
Figure 8. Typical Distribution of REF, FB Offset Current
Figure 5. Typical Distribution of Input Offset Current
Rev. A | Page 9 of 26
0.9
09945-007
200
200
09945-005
NUMBER OF HITS
21
09945-006
NUMBER OF HITS
500
09945-004
NUMBER OF HITS
600
AD8420
Data Sheet
10
0.3
1.5
0.2
1.0
0.1
0.5
0
0 –5
0
5
10
15
20
25
30
35
–0.1 40
INPUT VOLTAGE (V)
0
0
–10
–0.4
–15 –20
–15
INPUT COMMON-MODE VOLTAGE (V)
0.2
0
0
–1
–0.2
–2
0
5
10
15
–0.6 25
20
15
INPUT CURRENT (mA)
IIN
–5
Figure 12. Input Overvoltage Performance, G = 100, VS = ±15 V
0.4
1
–10
INPUT VOLTAGE (V)
VOUT
2
OUTPUT VOLTAGE (V)
0.2
–0.2
0.6
VS = ±15V G=1
5
–5
Figure 9. Input Overvoltage Performance, G = 1 3
0.4 IIN
VOUT
INPUT CURRENT (mA)
0.4
0.6
VS = ±15V G = 100
09945-312
IIN
2.0
15
OUTPUT VOLTAGE (V)
VOUT
0.5
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
VS = +5V G=1 = 0V V 2.5 V–IN = 0V REF
09945-309
3.0
–0.4
10
–1.0V, +12.3V
0.0V, +12.8V
+1.0V, +12.3V
5 0 MAXIMUM VDIFF = ±1V –5 –10 –15
–1.0V, –14.6V
+1.0V, –14.6V
–10
–5
0
5
10
15
20
–0.6 25
–20 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2
INPUT VOLTAGE (V)
Figure 10. Input Overvoltage Performance, G = 1, VS = ±15 V 6
0.3
3
0.2 VS = 5V G = 100 V–IN = 0V VREF = 0V
2
0.1
1
0 –5
INPUT CURRENT (mA)
4
0
0
5
10
15
20
25
30
35
INPUT VOLTAGE (V)
–0.1 40
09945-311
OUTPUT VOLTAGE (V)
0.4 IIN
0.4
0.6
0.8
1.0
1.2
3.0 INPUT COMMON-MODE VOLTAGE (V)
VOUT
0.2
Figure 13. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = ±15 V
0.5
5
0
OUTPUT VOLTAGE (V)
Figure 11. Input Overvoltage Performance, G = 100
2.5
+4mV, +2.8V +1.0V, +2.3V
2.0 1.5 MAXIMUM VDIFF = ±1V 1.0 0.5
+1.0V, +0.4V +4mV, –0.1V
0 –0.5 –0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT VOLTAGE (V)
Figure 14. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V, VREF = 0 V
Rev. A | Page 10 of 26
09945-314
–15
09945-310
–3 –20
09945-313
0.0V, –15.1V
Data Sheet 3.0
3.5
VREF = 2.5V RL = 10kΩ TO MIDSUPPLY
+2.5V, +2.8V
2.5 2.0
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
3.5
AD8420
+3.03V, +2.46V
+1.5V, +2.3V
1.5 MAXIMUM VFB = +VS – 2.2V 1.0 0.5
+1.5V, +0.4V +3.03V, +0.16V
0
3.0 2.5
+44mV, +2.8V
+4.8V, +2.78V
+44mV, –0.1V
+4.8V, –80mV
2.0 1.5 1.0 0.5 0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Figure 15. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 5 V, VREF = 2.5 V
Figure 18. Input Common-Mode Voltage vs. Output Voltage, G = 100, VS = 5 V, VREF = 0 V
0.6
3.5 +4mV, +0.5V INPUT COMMON-MODE VOLTAGE (V)
0.5 0.4 0.3 0.2
+0.6V, +0.2V
0.1 0
+4mV, –0.1V 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
OUTPUT VOLTAGE (V)
3.0 2.5
+86mV, +2.79V
+2.5V, +2.8V
+4.8V, +2.79V
+86mV, –90mV
+2.5V, –0.1V
+4.8V, –90mV
2.0
3.5
2.0 1.5 1.0 0.5 0 –0.5 –0.5
09945-316
–0.1 –0.2 –0.1
0
0.5
1.0
1.5
2.5
3.0
4.0
4.5
5.0
5.5
OUTPUT VOLTAGE (V)
Figure 16. Input Common-Mode Voltage vs. Output Voltage, G = 1, VS = 2.7 V, VREF = 0 V
Figure 19. Input Common-Mode Voltage vs. Output Voltage, G = 100, VS = 5 V, VREF = 2.5 V
20
0.6
15
+14.8V, +12.7V
–14.9V, +12.7V
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
0.0V, +12.8V
10 5 0 –5 –10 –15 –20 –20
0.0V, –15.1V +14.8V, –15.0V
–14.9V, –15.0V –15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
09945-317
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
–0.5 –0.5
Figure 17. Input Common-Mode Voltage vs. Output Voltage, G = 100, VS = ±15 V
+29mV, +0.5V
+2.53V, +0.49V
+29mV, –0.1V
+2.53V, –90mV
0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V)
Figure 20. Input Common-Mode Voltage vs. Output Voltage, G = 100, VS = 2.7 V, VREF = 0 V
Rev. A | Page 11 of 26
09945-319
1.8
09945-320
1.6
09945-315
–0.5 1.4
09945-318
+2.5V, –0.1V
AD8420
Data Sheet
40
120
–0.2V
POSITIVE PSRR (dB)
30 +2.7V
25 20 15
GAIN = 100 40 GAIN = 10 BANDWIDTH LIMIT
20
0
0.5
1.0
1.5
2.0
2.5
3.0
0 0.1
120
SPECIFIED PERFORMANCE RANGE
1k
NEGATIVE PSRR (dB)
0 –100 –200
GAIN = 100
80
60
BANDWIDTH LIMIT
40
GAIN = 10 GAIN = 1
IBIAS (–IN)
20
–1.0
–0.5
0
0.5
1.0
1.5
2.0
DIFFERENTIAL INPUT VOLTAGE (V)
0 0.1
09945-020
–1.5
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 22. Input Bias Current vs. Differential Input Voltage, VS = ±15
Figure 25. Negative PSRR vs. Frequency, RTI, VS = ±15 V
100
70
80
VS = ±15V
GAIN = 1000
60 50
GAIN = 100
40 GAIN (dB)
GAIN = 1000
60
GAIN = 100
40
GAIN = 10
100
10 GAIN = 1
–20
1k
10k
FREQUENCY (Hz)
100k
09945-500
10
GAIN = 10
20
–10
GAIN = 1 1
30
0
BANDWIDTH LIMIT
20
0 0.1
100k
GAIN = 1000
100
100
–400 –2.0
10k
VS = ±15V
200
–300
PSRR (dB)
100
Figure 24. Positive PSRR vs. Frequency, RTI, VS = ±15 V
400
IBIAS (+IN)
10
FREQUENCY (Hz)
Figure 21. Input Bias Current vs. Common-Mode Voltage
300
GAIN = 1 1
09945-323
IBIAS (+IN) IBIAS (–IN) COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (nA)
GAIN = 1000
60
09945-324
5 –2.0
80
–30 1
10
100
1k
10k
FREQUENCY (Hz)
Figure 26. Gain vs. Frequency
Figure 23. PSRR vs. Frequency on 5 V Supply
Rev. A | Page 12 of 26
100k
1M
09945-023
10
VS = ±15V
100
09945-019
INPUT BIAS CURRENT (nA)
35
Data Sheet
AD8420
70 60
120
VS = 2.7V
GAIN = 1000
100
50 GAIN = 100
80
30
CMRR (dB)
GAIN = 10
20 10
60
GAIN = 1
0
40
–10
20
–20 1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
VS = ±15V VCM = ±10V
0
09945-024
–30
0
0.1
VS = ±15V
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Figure 30. CMRR vs. Differential Input Voltage 120
BANDWIDTH LIMIT
0.3
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 27. Gain vs. Frequency, 2.7 V Single Supply 140
0.2
09945-329
GAIN (dB)
40
GAIN = 1000
VS = 5V
110
120
100 SUPPLY CURRENT (µA)
100 CMRR (dB)
GAIN = 100 80 60
GAIN = 10 GAIN = 1
40
90 80 70 60 50 40
20
1k
10k
100k
FREQUENCY (Hz)
20 –40
20
50
65
80
95
BIAS CURRENT (nA)
100 GAIN = 100 80 60
GAIN = 10 GAIN = 1
40
150 +IN BIAS CURRENT
15
100
10
50
5
FREQUENCY (Hz)
1k
10k
100k
0 –40
09945-328
100
125
Figure 29. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance, VS = ±15 V
200
–IN BIAS CURRENT
20
20
10
110
250
25
GAIN = 1000
1
35
30
120
CMRR (dB)
5
Figure 31. Supply Current vs. Temperature, VS = +5 V
VS = ±15V
0 0.1
–10
TEMPERATURE (°C)
Figure 28. CMRR vs. Frequency, RTI, VS = ±15 V 140
–25
0
OFFSET CURRENT
–25
–10
5
20
35
50
65
80
95
110
–50 125
TEMPERATURE (°C)
Figure 32. Input Bias Current and Input Offset Current vs. Temperature
Rev. A | Page 13 of 26
09945-331
100
OFFSET CURRENT (pA)
10
09945-327
1
09945-027
30
0 0.1
AD8420
Data Sheet 200
OFFSET CURRENT (pA)
20
100 +IN BIAS CURRENT
15
50
10
0 OFFSET CURRENT
5
OFFSET VOLTAGE (µV)
150
–IN BIAS CURRENT
–50
–25
–10
5
20
35
50
65
80
95
110
200 100 0 –100 –200 –300
–100 125
–400 –40
TEMPERATURE (°C)
–25
–10
5
1000
5
VIN = ±1V 800 VS = ±15V
4
0 PART B
–200
80
95
110
125
REPRESENTATIVE DATA NORMALIZED AT 25°C
VS = ±15V
1
PART A: 0.024ppm/°C
0 –1
–400
–2
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
–4 –40
09945-333
–1000 –40
PART B: 0.038ppm/°C
–3
REPRESENTATIVE DATA NORMALIZED TO 25ºC
20
35
50
65
80
+VS
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
VIN = ±0.1V 800 VS = ±15V 600 400 PART A 200 0
–200 PART B
–600 REPRESENTATIVE DATA NORMALIZED TO 25ºC –10
5
20
35
TEMPERATURE (°C)
50
65
80
95
110
125
RL = 20kΩ
–0.1 –0.2 –0.3 –40°C +25°C +85°C +125°C +0.3 +0.2 +0.1 –VS
09945-334
–25
5
Figure 37. CMRR vs. Temperature, G = 1, VS = ±15 V
1000
–1000 –40
–10
TEMPERATURE (°C)
Figure 34. Gain Error vs. Temperature, G = 1, VIN = ±1 V, VS = ±15 V
–400
–25
09945-032
–600
GAIN ERROR (µV/V)
65
2
200
–800
50
3
PART A CMRR (µV/V)
GAIN ERROR (µV/V)
600
–800
35
Figure 36. Offset Drift
Figure 33. FB, REF Bias Current and FB, REF Offset Current vs. Temperature
400
20
TEMPERATURE (°C)
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±VS)
Figure 38. Output Voltage Swing vs. Supply Voltage, RL = 20 kΩ
Figure 35. Gain Error vs. Temperature, G = 1, VIN = ±0.1 V, VS = ±15 V
Rev. A | Page 14 of 26
09945-035
0 –40
NORMALIZED TO 25°C
300
09945-332
BIAS CURRENT (nA)
25
400
09945-031
30
AD8420
+VS
+VS
–0.2
–0.2 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
–0.4 –0.6 –0.8
–40°C +25°C +85°C +125°C
+0.8 +0.6 +0.4
VS = 5V VREF = 2.5V
+0.2
–0.4 –0.6 –40°C +25°C +85°C +125°C
–0.8
+0.8 +0.6 +0.4 +0.2
10k
100k
1M
LOAD RESISTANCE (Ω)
–VS 0.1
09945-338
–VS 1k
09945-340
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
Data Sheet
1 OUTPUT CURRENT (mA)
Figure 39. Output Voltage Swing vs. Load Resistance, VS = 5 V
Figure 42. Output Voltage Swing vs. Output Current, VS = ±15
+VS
2k 1k
–0.4 –0.6 –0.8
NOISE (nV/ Hz)
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
–0.2
–40°C +25°C +85°C +125°C
+0.8 +0.6 +0.4
GAIN = 1
100 GAIN = 10
VS = 5V VREF = 2.5V
1 OUTPUT CURRENT (mA)
Figure 40. Output Voltage Swing vs. Output Current, VS = 5 V
20 0.1
GAIN = 100 1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 43. Voltage Noise Spectral Density vs. Frequency, RTI
15
5
0
–40°C +25°C +85°C +125°C
–10
–15 1k
10k
100k
1M
LOAD RESISTANCE (Ω)
0.4µV/DIV
1s/DIV
Figure 41. Output Voltage Swing vs. Load Resistance, VS = ±15 V
Figure 44. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1
Rev. A | Page 15 of 26
09945-043
–5
09945-339
OUTPUT VOLTAGE SWING (V)
10
09945-042
–VS 0.1
09945-501
+0.2
AD8420
Data Sheet VS = ±5V
1V/DIV 1.78µs TO 0.1% 3.31µs TO 0.01%
100
0.02%/DIV
1
10
100
1k
10k
100k
FREQUENCY (Hz)
09945-348
20µs/DIV 10
09945-149
NOISE (fA/ Hz)
1k
Figure 45. Current Noise Spectral Density vs. Frequency
Figure 48. Large Signal Pulse Response and Settling Time, G = 1 VS = ±5V
4.5V/DIV 67µs TO 0.1% 138µs TO 0.01%
1s/DIV
200µs/DIV
Figure 49. Large Signal Pulse Response and Settling Time, G = 10
Figure 46. 0.1 Hz to 10 Hz Current Noise 30
VS = ±5V
VS = ±15V, G = 15V/V
27
09945-150
1.5pA/DIV
09945-147
0.02%/DIV
21 18
4.5V/DIV 600ms TO 0.1% 1.04ms TO 0.01%
15 12
0.02%/DIV
9
VS = +5V, G = 5V/V
3
20ms/DIV
0 1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
09945-151
6
09945-148
OUTPUT VOLTAGE (V p-p)
24
Figure 50. Large Signal Pulse Response and Settling Time, G = 100
Figure 47. Large Signal Frequency Response
Rev. A | Page 16 of 26
4µs/DIV
20mV/DIV
Figure 51. Small Signal Pulse Response, G = 1, RL = 20 kΩ, CL = 100 pF
2ms/DIV
09945-054
20mV/DIV
AD8420
09945-051
Data Sheet
Figure 54. Small Signal Pulse Response, G = 1000, RL = 20 kΩ, CL = 100 pF
NO LOAD 220pF 470pF
20µs/DIV
20mV/DIV
09945-055
20mV/DIV
09945-052
780pF
5µs/DIV
Figure 55. Small Signal Response with Various Capacitive Loads, G = 1, RL = ∞
Figure 52. Small Signal Pulse Response, G = 10, RL = 20 kΩ, CL = 100 pF
90
SUPPLY CURRENT (µA)
85
75 70 65 60 55 50 0
5
10
15
20
25
30
35
SUPPLY VOLTAGE (V)
Figure 53. Small Signal Pulse Response, G = 100, RL = 20 kΩ, CL = 100 pF
Rev. A | Page 17 of 26
Figure 56. Supply Current vs. Total Supply Voltage
40
09945-057
200µs/DIV
09945-053
20mV/DIV
80
AD8420 90 –20
Data Sheet
TESTED WITH DUAL SUPPLIES CENTERED AT 0V
–60 –80 –100 –120 –140 –160 –180 –200 0
4
8
12
16
20
24
28
SUPPLY VOLTAGE (V)
32
36
09945-502
OFFSET VOLTAGE (µV)
–40
Figure 57. Offset Voltage vs. Total Supply Voltage
Rev. A | Page 18 of 26
Data Sheet
AD8420
THEORY OF OPERATION AD8420
+VS
– +
A
VOUT
I3
–VS +VS
Vb
FB gm1
–IN
R2 –
ESD PROTECTION gm2 I1
ESD PROTECTION
–VS +VS
R1 +
I2
REF –VS
09945-058
+IN
Figure 58. Simplified Schematic
ARCHITECTURE
Table 7. Suggested Resistors for Various Gains, 1% Resistors
The AD8420 is based on an indirect current feedback topology consisting of three amplifiers: two matched transconductance amplifiers that convert voltage to current and one integrator amplifier that converts current to voltage.
R1 (kΩ) None 49.9 20 10 5 2 1 1 1 1
I3 is integrated to the output, making the output voltage, VOUT, increase. This voltage continues to increase until the same differential input voltage across the inputs of gm1 is replicated across the inputs of gm2, generating a current (I2) equal to I1. This reduces the Difference Current I3 to zero so that the output remains at a stable voltage. The gain in the configuration shown in Figure 58 is set by R2 and R1. In traditional instrumentation amplifiers, the input commonmode voltage can limit the available output swing, typically depicted in a hexagon plot. Because the AD8420 converts the input differential signals to current, this limit does not apply. This is particularly important when amplifying a signal with a commonmode voltage near one of the supply rails.
While the ratio of R2 to R1 sets the gain, the designer determines the absolute value of the resistors. Larger values reduce power consumption and output loading; smaller values limit the FB input bias current and offset current error. For best output swing and distortion performance, keep (R1 + R2) || RL ≥ 20 kΩ. A method that allows large value feedback resistors while limiting FB bias current error is to place a resistor of value R1 || R2 in series with the REF terminal, as shown in Figure 59. At higher gains, this resistor can simply be the same value as R1.
To improve robustness and ease of use, the AD8420 includes differential voltage protection to limit the current into its inputs to a safe level. This protection scheme allows wide differential input voltages without damaging the device.
+IN
AD8420
IB–
FB –IN
R2 R1
+ R1||R2 – VREF
VOUT = G(V+IN − V−IN) + VREF
REF
IB F
R1
R2
IB R
G=1+
The transfer function of the AD8420 is
VOUT
IB +
SETTING THE GAIN
where G 1
Gain 1.00 2.00 5.03 10.09 20.06 49.8 101 201 500 1001
09945-059
For the AD8420, assume that all initial voltages and currents are zero until a positive differential voltage is applied between the inputs, +IN and −IN. Transconductance Amplifier gm1 converts this input voltage into a current, I1. Because the voltage across gm2 is initially zero, I2 is zero and I3 equals I1.
R2 (kΩ) Short 49.9 80.6 90.9 95.3 97.6 100 200 499 1000
Figure 59. Cancelling Out Error from FB Input Bias Current
R2 . R1
Rev. A | Page 19 of 26
AD8420
Data Sheet
GAIN ACCURACY
INPUT PROTECTION
Unlike most instrumentation amplifiers, the relative match of the two gain setting resistors determines the gain accuracy of the AD8420 rather than a single resistor. For example, if two resistors have exactly the same absolute error, there is no error in gain. Conversely, two 1% resistors can cause approximately 2% maximum gain error at high gains. Temperature coefficient mismatch of the gain setting resistors increases the gain drift of the instrumentation amplifier circuit, according to the gain equation. Because these external resistors do not have to match any on-chip resistors, resistors with good TC tracking can achieve excellent gain drift. Even with standard thin film resistors, the AD8420 can still achieve better gain drift than most instrumentation amplifiers.
The current into the AD8420 inputs is limited internally. This ensures that the diodes that limit the differential voltage seen by the internal amplifier do not draw excessive current when they turn on. The device can handle large differential input voltages, regardless of the amount of gain applied, without damage. As a result, the AD8420 inputs are protected from voltages beyond the positive rail. If voltages beyond the negative rail are expected, external protection must be used.
When the differential voltage at the inputs approaches the differential input limit, the diodes start to conduct, limiting the voltage seen by the inputs of amplifier gm1. This can look like increased gain error at large differential inputs. Performance of the AD8420 is specified for ±1 V differential from −40°C to +85°C. However, at higher temperatures, the reduced forward voltage of the diodes limits the differential input to a smaller voltage. Figure 60 tracks 1% error across the operating temperature range to show the effect of temperature on the input limit. VS = ±15V
For applications that require protection beyond the negative rail, one option is to use an external resistor in series with each input to limit current during overload conditions. In this case, size the resistors to limit the current into the AD8420 to 6 mA. RPROTECT ≥ (Negative Supply − VIN)/6 mA Although the AD8420 inputs must still be kept within the −VS + 40 V limitation, the I × R drop across the protection resistor increases the protection on the positive side to approximately (40 V + Negative Supply) + 300 μA × RPROTECT An alternate protection method is to place diodes at the AD8420 inputs to limit voltage and resistors in series with the inputs to limit the current into these diodes. To keep input bias current at a minimum for normal operation, use low leakage diode clamps, such as the BAV199. The AD8420 also combines well with TVS diodes, such as the PTVSxS1UR.
1.8 1.6 1.4
Input Voltages Beyond the Rails
POSITIVE VOLTAGE
1.2 1.0 0.8
RPROTECT
0.6
+ VIN+ –
0.4 0.2 0 –40
AD8420 RPROTECT
–25
–10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
125
+ VIN– –
Figure 60. Differential Input Limit vs. Temperature
+VS RPROTECT
+VS
I
+ VIN+ –
–VS +VS
AD8420
RPROTECT –VS
+ VIN– –
SIMPLE METHOD
INPUT VOLTAGE RANGE
–VS
–VS
ALTERNATE METHOD
Figure 61. Protection for Voltages Beyond the Rails
The allowed input range of the AD8420 is much simpler than traditional architectures. For the transfer function of the AD8420 to be valid, the input voltage should follow two rules:
+VS
09945-160
NEGATIVE VOLTAGE
09945-503
MAXIMUM INPUT VOLTAGE (1% ERROR)
2.0
Keep all of the AD8420 terminals within the voltage range specified in the Absolute Maximum Ratings section. All terminals of the AD8420 are protected against ESD.
Keep the differential input voltage within ±1 V. Keep the voltage on the +IN, −IN, REF, and FB pins in the specified input voltage range.
Because the output swing is completely independent of the input common-mode voltage, there are no hexagonal figures or complicated formulas to follow, and no limitation for the output swing the amplifier has for input signals with changing common mode.
Large Differential Input Voltage The AD8420 is able to handle large differential input voltage without damage to the device. Refer to Figure 9, Figure 10, Figure 11, and Figure 12 for overvoltage performance. The AD8420 differential voltage is internally limited with diodes to ±1 V. If this limit is exceeded, the diodes start to conduct and draw current, as shown in Figure 22. This current is limited internally to a value that is safe for the AD8420, but if the input current cannot be tolerated in the system, place resistors in series with each input with the following value:
Rev. A | Page 20 of 26
1V 1 V RPROTECT DIFF 2 I MAX
Data Sheet
AD8420
LAYOUT
Reference
Common-Mode Rejection Ratio over Frequency
The output voltage of the AD8420 is developed with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local ground. The differential voltage at the inputs is reproduced between the REF and FB pins; therefore, it is important to set VREF so that the voltage at FB does not exceed the input range.
Poor layout can cause some of the common-mode signal to be converted to a differential signal before reaching the in-amp. This conversion can occur when the path to the positive input pin has a different frequency response than the path to the negative input pin. For best CMRR vs. frequency performance, the input source impedance and capacitance of each path should be closely matched. This includes connecting Pin 1 to −VS, which matches the parasitic capacitance and the leakage between the inputs and adjacent pins. Place additional source resistance in the input path (for example, for input protection) close to the in-amp inputs to minimize their interaction with the parasitic capacitance from the printed circuit board (PCB) traces.
DRIVING THE REFERENCE PIN Traditional instrumentation amplifier architectures require the reference pin to be driven with a low impedance source. In these architectures, impedance at the reference pin degrades both CMRR and gain accuracy. With the AD8420 architecture, resistance at the reference pin has no effect on CMRR. +IN VOUT
Power Supplies
AD8420
Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. For more information, see the PSRR performance curves in Figure 24 and Figure 25.
+VS
G=1+
R2 + RREF R1
R1
RREF
R2
09945-062
Place a 0.1 μF capacitor as close as possible to each supply pin. As shown in Figure 62, a 10 μF tantalum capacitor can be used farther away from the device. This capacitor, which is intended to be effective at low frequencies, can usually be shared by other precision integrated circuits. Keep the traces between these integrated circuits short to minimize interaction of the trace parasitic inductance with the shared capacitor.
FB REF
–IN
VREF
Figure 63. Calculating Gain with Reference Resistance
Resistance at the reference pin does affect the gain of the AD8420, but if this resistance is constant, the gain setting resistors can be adjusted to compensate. For example, the AD8420 can be driven with a voltage divider to level shift the output as shown in Figure 64. +IN
0.1µF
10µF
VOUT
AD8420
+IN
FB VOUT
AD8420
VS R2
G=1+
–VS
10µF
R2
R2 + R3||R4 R4 R1
Figure 64. Using Resistor Divider to Set Reference Voltage
09945-060
0.1µF
R1
R3 09945-063
R1
–IN
REF
–IN
Figure 62. Supply Decoupling, REF, and Output Referred to Local Ground
Rev. A | Page 21 of 26
AD8420
Data Sheet INCORRECT
CORRECT
+VS
+VS
VOUT
VOUT
AD8420
AD8420
–VS
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
VOUT
VOUT
AD8420
AD8420
10MΩ –VS
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+VS
C
C VOUT
AD8420
VOUT
1 R fHIGH-PASS = 2πRC
C
AD8420
C
–VS
09945-061
R –VS
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 65. Creating an IBIAS Path +VS
INPUT BIAS CURRENT RETURN PATH
0.1µF R 20kΩ 1% +IN
RADIO FREQUENCY INTERFERENCE (RFI) –IN
All instrumentation amplifiers can rectify high frequency out-ofband signals. Once rectified, these signals appear as dc offset errors at the output. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 66. The filter limits the input signal bandwidth according to the following relationship:
FilterFrequency DIFF FilterFrequency CM where CD 10 CC.
1 2πR(2C D C C )
1 2πRCC
10µF
CC 330pF 5%
R CD 20kΩ 3300pF 1%
VOUT
AD8420
CC 330pF 5%
R1 0.1µF
R2
10µF –VS
09945-064
The input bias current of the AD8420 must have a return path to ground. When the source, such as a thermocouple, cannot provide a return current path, create one, as shown in Figure 65.
Figure 66. Suggested RFI Suppression Filter
CD affects the differential signal and CC affects the common-mode signal. Values of R and CC are chosen to minimize out of band RFI at the expense of reduced signal bandwidth. Mismatch between the R × CC at the positive input and the R × CC at the negative input degrades the CMRR of the AD8420. By using a value of CD that is at least one magnitude larger than CC, the effect of the mismatch is reduced and performance is improved.
Rev. A | Page 22 of 26
Data Sheet
AD8420
OUTPUT BUFFERING The AD8420 is designed to drive loads of 20 kΩ or greater but can deliver up to 10 mA to heavier loads at lower output voltage swings (see Figure 42). If more output current is required, buffer the AD8420 output with a precision op amp. Figure 67 shows the recommended configuration using the ADA4692-2 with a single supply. This low power op amp can swing its output from 1 V to 4 V on a single 5 V supply while sourcing or sinking more than 30 mA of current. When using this configuration, the load seen by the AD8420 is approximately R1 + R2. +5V
+VS 0.1µF
AD8420 ADA4692-2 –VS
R1
VOUT
R2
VIN
VREF –VS
09945-065
VIN
+5V 0.1µF
AD8420
VOUT
0.1µF
CW R1
R2
R
W
REF
Figure 67. Output Buffering
ADA4692-2 SUGGESTION FOR SECOND AMPLIFIER: VARIABLE LEVEL SHIFT WITHOUT AFFECTING GAIN
Figure 68. Variable Level Shift
Rev. A | Page 23 of 26
CCW
R 09945-066
+VS
0.1µF
Because the ADA4692-2 is a dual op amp, another op amp is now free for use as an active filter stage or to buffer another AD8420 output on the same PCB. Figure 68 shows another suggestion for how to use this second op amp. In this circuit, the voltage from the wiper of a potentiometer is buffered by the ADA4692-2, allowing a variable level shift of the output. Resistors above and below the potentiometer reduce the total range of the level shift but increase the precision. If the potentiometer were connected directly to the REF pin of the AD8420, gain error would be introduced from the variable resistance. The potentiometer can be tuned in hardware or software, depending on the type of potentiometer chosen. For a list of digital potentiometers made by Analog Devices, Inc., visit www.analog.com/digitalpotentiometers.
AD8420
Data Sheet
APPLICATIONS INFORMATION A high-pass filter is commonly used in ECG signal conditioning circuitry to remove electrode offset and motion artifacts. To avoid degrading the input impedance and CMRR of the system, this filtering is typically implemented after the instrumentation amplifier, which limits the gain that can be applied with the instrumentation amplifier. With a 3-op-amp instrumentation amplifier, gain is applied in the first stage. Because of this, the electrode offset is gained and then must be removed afterward with a high-pass filter. In the AD8420 architecture, the offset can be accounted for in the input stage
200pF A
B
402kΩ
Figure 69 shows an ECG front end that applies a gain of 100 to the signal while rejecting dc and high frequencies. This circuit combines the AD8420 with the AD8657, which is a low power, low cost, dual, precision CMOS op amp.
THREE-POLE LPF, BESSEL RESPONSE FC = 50Hz
INSTRUMENTATION AMPLIFIER G = +100 +5V
100kΩ 2000pF
500kΩ
by unbalancing the transconductance amplifier at the REF and FB pins. In the steady state, the offset at the input is not gained to the output, and higher frequency signals can be gained and passed through. Using the AD8420 in this way, the offset tolerance is nearly the differential input range of the device (±1 V).
AD8420
100kΩ 200pF
FB
REF –5V
C
110kΩ
200kΩ
0.015μF
0.022μF
200kΩ
+5V
100kΩ 1kΩ
3.3μF +5V
8200pF 10MΩ –5V
AD8657-1 –5V
Figure 69. AD8420 in an ECG Front End
Rev. A | Page 24 of 26
AD8657-2
INTEGRATOR PROVIDES HIGH-PASS POLE AT 0.5Hz
09945-072
AD8420 IN ELECTROCARDIOGRAPHY (ECG)
Data Sheet
AD8420
CLASSIC BRIDGE CIRCUIT
4 mA TO 20 mA SINGLE-SUPPLY RECEIVER
Figure 70 shows the AD8420 configured to amplify the signal from a classic resistive bridge. This circuit works in dual-supply mode or single-supply mode. Typically, the same voltage that powers the instrumentation amplifier excites the bridge. Connecting the bottom of the bridge to the negative supply of the instrumentation amplifier sets up an input common-mode voltage that is located midway between the supply voltages. The voltage on the REF pin can be varied to suit the application. For example, the REF pin is tied to the VREF pin of an analog-to-digital converter (ADC) whose input range is (VREF ± VIN). With an available output swing on the AD8420 of (−VS + 100 mV) to (+VS − 150 mV), the maximum programmable gain is simply this output range divided by the input range.
The 90 μA maximum supply current, input range that goes below ground, and low drift characteristics make the AD8420 a very good candidate for use in a 4 mA to 20 mA loop. Figure 71 shows how a signal from a 4 mA to 20 mA transducer can be interfaced to the AD8420. The signal from a 4 mA to 20 mA transducer is single-ended, which initially suggests the need for a simple shunt resistor to ground to convert the current to a voltage. However, any line resistance in the return path (to the transducer) adds a current-dependent offset error; therefore, the current must be sensed differentially. In this example, a 5 Ω shunt resistor generates a differential voltage at the inputs of the AD8420 between 20 mV (for 4 mA in) and 100 mV (for 20 mA in) with a very low common-mode value. With the gain resistors shown, the AD8420 amplifies the 100 mV input voltage by a factor of 40 to 4.0 V.
+VS 0.1µF
VDIFF
AD8420
VOUT
VREF 09945-069
0.1µF –VS
Figure 70. Classic Bridge Circuit
5V 0.1µF – LINE IMPEDANCE +
– + POWER SUPPLY
4mA TO 20mA
5Ω
AD8420 AD627 G = 40
R2 = 97.6kΩ R1 = 2.49kΩ
Figure 71. 4 mA to 20 mA Receiver Circuit
Rev. A | Page 25 of 26
R1
R2
0.8V TO 4.0V
09945-073
4mA TO 20mA TRANSDUCER
AD8420
Data Sheet
OUTLINE DIMENSIONS 3.20 3.00 2.80
8
3.20 3.00 2.80
1
5.15 4.90 4.65
5
4
PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75
15° MAX 1.10 MAX
0.40 0.25
6° 0°
0.23 0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80 0.55 0.40 10-07-2009-B
0.15 0.05 COPLANARITY 0.10
Figure 72. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE Model1 AD8420ARMZ AD8420ARMZ-R7 AD8420ARMZ-RL 1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C
Package Description 8-Lead Mini Small Outline Package [MSOP], Tube 8-Lead Mini Small Outline Package [MSOP], 7-Inch Tape and Reel 8-Lead Mini Small Outline Package [MSOP], 13-Inch Tape and Reel
Z = RoHS Compliant Part.
©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09945-0-1/15(A)
Rev. A | Page 26 of 26
Package Option RM-8 RM-8 RM-8
Branding Y3Y Y3Y Y3Y
