Wimedia Mac-phy Interface

Transcript

Larry Taylor Allan Bjerke System Architect Sr. Hardware Engineer Staccato Communications Intel Corporation MAC-PHY Interface • Simple State Machine Model • Synchronous Interface • Minimum Number of Signal Lines • Sleep & Active States • Flexible Expression of Frame Exchange and IFS Control 2 Interface Signals PHY • Four Signal Groups • • • • Control Interface Data Interface CCA Interface Management Interface Control Interface MAC PHY_RESET TX_EN RX_EN PHY_ACTIVE STOPC Data Interface PCLK DATA_EN DATA[7:0] CCA Interface CCA_STATUS Management Interface SERIAL_DATA 3 PHY Reset • PHY can be reset at any time and from any state PHY_RESET Note: PHY_ACTIVE is asserted by the PHY while PHY _RESET is asserted . RESET • PHY_RESET asserted for PHY specific duration PHY_ACTIVE is de -asserted and transition to STANDBY occurs when PHY_RESET operations have completed • PHY_ACTIVE asserted by PHY • PCLK may be off or undefined PMMode = SLEEP SLEEP STANDBY PMMode = STANDBY TX_EN & RX _EN • PHY_ACTIVE de-asserted to signal stable PCLK and STANDBY state PMMode = SLEEP • Check RDY register in CONTROL PMMode = STANDBY PMMode = READY TX_EN & RX _EN TRANSMIT TX_EN & RX _EN READY RECEIVE PHY_RESET TX_EN & RX _EN TX_EN & RX _EN & PHY_ACTIVE PHY_ACTIVE PCLK 4 Exit From Sleep • PCLK is off • Wake action via TX_EN & RX_EN PHY_RESET RESET • PHY_ACTIVE asserted when in STANDBY state • MAC Handshake Completion by de-asserting TX_EN & RX_EN Note: PHY_ACTIVE is asserted by the PHY while PHY_RESET is asserted. PHY_ACTIVE is de-asserted and transition to STANDBY occurs when PHY_RESET operations have completed PMMode = SLEEP SLEEP STANDBY PMMode = STANDBY TX_EN & RX_EN PMMode = SLEEP PCLK PMMode = STANDBY PMMode = READY TX_EN TX_EN & RX_EN RX_EN TRANSMIT READY PHY_ACTIVE STATE SLEEP UNDEFINED STANDBY TX_EN & RX_EN TX_EN & RX_EN & PHY_ACTIVE RECEIVE TX_EN & RX_EN 5 Register Set • Ranging Timer • • • • • PHY State Receive Control Transmit Control Regulatory Control 6 Register Access Timing PHY reads Tx Control Registers during TxHoldTime TxSetupTime • Transmit TX_EN MAC may write Tx Control Registers at any time except TxSetupTime or TxHoldTime TxHoldTime RxHoldTime PHY reads Rx Control Registers RX_EN • Receive RxSetupTime MAC writes Rx Control Registers RxSetupTime PHY_ACTIVE RxHoldTime 7 Frame Format Rx Frame Tx Frame B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 • Control fields Octet 0 Octet 1 • PHY Header • Immediate Header Status RT5 RT4 DataRate RT3 RT2 RT1 R2 R1 Length [7 :0] MSB15 Octet 0 LSB 8 Octet 2 S2 S1 R4 R3 MSB Length [11:8] 19 Octet 3 BG T3 T2 T1 PT BM R6 Octet 4 R14 R13 R12 R11 R10 R9 Octet 5 R0 R8 Octet 1 • Frame Body & FCS • Rx Status Octet LENGTH+18 DataRate RT3 RT2 MSB15 RT1 R2 R1 R0 Length [7 :0] LSB 8 R4 R3 MSB Length [11:8 ] LSB 19 16 T2 PT BM R6 R5 Octet 2 R5 Octet 3 BG T3 R7 Octet 4 R14 R13 R12 R11 R10 R9 R8 R7 Octet 5 MAC Header Octet 15 Octet LENGTH+15 RT4 LSB 16 MAC Header Octet 15 MAC Frame Payload Octet m RT5 S2 Not Used FCS [24:31] MSB 31 LSB 16 FCS [16:23] MSB 23 LSB 8 FCS [8:15] MSB 15 LSB 0 FCS [0:7] MSB 7 Octet LENGTH+16 Octet LENGTH+19 T1 B4 HeaderError [4 :0 ] B3 B2 B1 B0 MAC Frame Payload Octet m LSB 24 S1 LSB 24 FCS[24:31] MSB 31 LSB 16 FCS[16:23] MSB 23 LSB 8 FCS[8:15] MSB 15 LSB 0 FCS[0:7] MSB 7 RSSI[7:0] LQI[7:0] PLCP Header LENGTH (12 bits) RATE (5 bits) R R R 0 1 2 RT1 RT2 RT3 RT4 RT5 3 4 5 6 7 LSB 8 SCRAMBLER (2 bits) BURST MODE (2 bits) BA ND GROUP LSB (1bit) Tx TFC (3 bits) MSB R R S1 S2 R R BM PT T1 T2 T3 BG Octet LENGTH+22 Not Used B4 RxError [4 :0] B3 B2 B1 B0 R : Reserved R R R R R R R R 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 8 Theory of Operation • TX_EN, RX_EN & PHY_ACTIVE encode all interface semantics • All signals are synchronous to rising edge of PCLK • DATA[7:0] is qualified by DATA_EN • PHY_ACTIVE provides accurate on-air beginning of frame and end of frame timing from PHY to MAC • Tx and Rx offsets to compensate for PHY processing delays • No ‘handshake’ between PHY and MAC to indicate when status bytes are being passed • MAC counts bytes to determine when the status bytes have arrived (mostly) 9 Transmit Delay Intervals • TxDelay transmit delay path constant • TxDataDelay for extra MAC processing time • Explicit end of frame timing TxDelay MAC indicates end of frame data TX_EN PHY indicates end of frame on air PHY_ACTIVE TxDataDelay MAC-PHY I/F Header MAC Frame Payload RADIO MEDIUM Standard Preamble STATE READY Header MAC Frame Payload TRANSMIT READY 10 Single Frame Transmit • TX_EN assertion + TxDelay defines start of frame on air • Explicit end of frame timing • TX_EN de-assertion signals end of MAC data PCLK TX_EN End of Frame at local antenna RX_EN PHY_ACTIVE DATA[7:0] XX XX D0 D1 XX D2 D3 Dn-1 Dn XX XX DATA_EN STATE READY DATA[7:0] Driven by PHY Note change in bus ownership TRANSMIT READY DATA[7:0] Driven by MAC DATA[7:0] Driven by PHY 11 Burst Mode Transmit • TX_EN re-assertion at least TxDelay before MIFS expires • Minimum 3 PCLK cycles off time • PHY enforced 6 symbol IFS TX_EN de-asserted for at least 3 PCLKs Window in which the MAC can reassert TX_EN TxDelay TX_EN TxDelay PHY_ACTIVE MAC-PHY I/F RADIO MEDIUM Header Standard Preamble MAC Frame Data Header Header MAC Frame Data Burst Preamble MAC Frame Data Header MAC Frame Data MIFS 12 Receive Delay Intervals • RxDelay receive path delay constant • PHY_ACTIVE assertion provides Rx Timestamp • SyncDelay receive timing reference • PHY_ACTIVE de-assertion provides end of frame timing • PhyActiveDelay decode path constant RxDelay PhyActiveDelay RX_EN PHY_ACTIVE Begin Acquisition MAC-PHY I/F End of Preamble Packet/Frame Synchronization Sequence Header MAC Frame Data RADIO MEDIUM Standard Preamble STATE STANDBY READY SyncDelay Header MAC Frame Data RECEIVE READY 13 Single Frame Receive • RxDelay receive path delay constant • PHY_ACTIVE assertion provides Rx Timestamp • SyncDelay receive timing reference • PHY_ACTIVE de-assertion provides end of frame timing • PhyActiveDelay decode path constant PCLK TX_EN RX_EN End of Frame Sync Seq at local antenna PHY_ACTIVE End of Frame at local antenna SyncDelay XX DATA[7:0] D0 D1 XX D2 D3 PhyActiveDelay Dn- 1 Dn XX DATA_EN STATE READY Note SyncDelay & PHYActiveDelay wrt PHY timing RECEIVE READY DATA[7:0] Driven by PHY 14 Burst Mode Receive • RX_EN maintained asserted during Burst Mode Receive • PLCP Header signals subsequent frame preamble and burst continuation • Usual start and end of frame timing via PHY_ACTIVE, SyncDelay and PHYActiveDelay SyncDelay PhyActiveDelay SyncDelay PhyActiveDelay PHY_ACTIVE MAC-PHY I/F Radio Medium Header Long Preamble Header Frame Data Frame Data MIFS Header Short Preamble Header Frame Data Frame Data 15 Preamble Control • PT & BM • PT & BM in PLCP Header • Burst Mode only • Long or short preamble Previous Burst or Single Frame Transmission BM=0 PT=0 Frame (m) BM=1 PT=0 or PT=1 Frame (m+1) BM=1 PT=0 or PT=1 Frame (n-1) BM=1 PT=0 or PT=1 Frame (n) BM=0 PT=0 Frame (n+1) xx xx Burst Transmission • PTON • Receive override PT processing Frame (m-1) Next Burst or Single Frame Transmission 16 Zero Length Frame Rx • PHYActiveDelay allows accurate end-of-frame-on-air timing • Frame status bytes follow header status byte on data lines • Flow-controlled by DATA_EN • MAC knows to expect them because length was zero SyncDelay PHYActiveDelay PHY_ACTIVE MAC-PHY I/F Radio Medium Header Preamble Header PCLK DATA_EN MAC-PHY I/F Last bytes of Header Header Error RSSI LQI RX Error 17 18