Ymu809 Catalog

Transcript

TM YMU809 MC-3 Mobile Codec 3 „ OUTLINE The YMU809(MC-3) is an Audio CODEC chip developed for portable devices such as mobile phones, PNDs (Personal Navigation Device), which realizes voice source processing including hands-free capability and sound quality improvement of audio sources using AudioEngine(TM) technique. (MC-3 is another name for representing the functions of YMU809.) As for voice source processing, this device realizes high-performance hands-free capability by Echo Canceller, Noise Suppressor, etc. which was optimized even for a constrained reproduction environment as in a mobile terminal with a small diameter speaker. And, Noise Suppressor is applicable to both transmitter and receiver sides, which allows clearer voice to be sent to both sides by combining speech speed control function and voice quality improvement function using AudioEngine(TM) technique. And for sound quality improvement of audio sources, DSP processing using AudioEngine(TM) technique realizes high-performance and high-sound-quality audio processing functions such as Surround Sound Field Processing (including 2ch-5ch-2ch conversion), Bass Boost, Digital Equalizer, and Dynamic Range Controller. In addition, the YMU809 (MC-3) has decoders for a variety of compressed audio formats: MP3, Enhanced HE AAC, WMA, ATRAC3, etc., which is suitable for low-power consumption mobile phones and mobile audio devices. The YMU809 (MC-3) has an easy-to-use configuration that integrates the following audio-related peripherals: Stereo ADC/DAC, Stereo Headphone Amplifier, Receiver Amplifier, Separate 2-line Digital Audio I/O, 3-line Microphone Inputs, Analog I/O, Mixers, Volumes, etc. Moreover, power-down mode allows a block to be separately powered down when unused and this minimizes the consumption current. Thus, the YMU809 (MC-3) is the optimum I/O device for various sound sources handled in mobile devices such as voices for mobile phones, PND, camcorder, etc. and audio sound signals for music, analog/digital TV, radio, etc. YMU809 CATALOG CATALOG No : LSI-4MU809A20 2009. 5 YMU809 „ FEATURES □ Processing of voice source, improvement of its sound quality ● Noise suppressor and echo canceller for hands-free processing ● Noise suppressor is applicable to both transmitter and receiver sides ● Speech speed control ● Improvement processing of voice quality ● Side-tone processing □ Improvement of audio-source sound quality ● Surround processing such as 2ch-5ch-2ch ● Sound enhancer ● Bass boost ● 10-band digital equalizer ● Dynamic range controller ● Sound field controller ● Multifunctional effectors ● Vocal canceller, pitch changer for Karaoke function □ Decode of various compressed audio formats, improvement of their sound quality ● Decoder: MP3 / AAC / HE AAC / Enhanced HE AAC / WMA / ATRAC3 / AMR / G.726 / PCM / SBC ● Encoder: AMR / PCM / SBC ● Sound quality improvement processing for compressed audio playback □ Comprehensive management of sound output, and adapt to various programming environments ● 16-bit AD/DA converter ● Multifunctional mixer ● Digital audio input interface (2 stereo lines, separately) ● Digital audio output interface (2 stereo lines, separately) ● Sampling frequency auto-detect function for digital audio inputs/outputs ● Microphone inputs (3 lines) ● 8-bit parallel CPU I/F ● General-purpose I/O port ● Stereo analog inputs (2 lines, differential input is possible) ● Stereo analog output (1 line, differential output is possible) ● Monaural analog output (1 line) ● Stereo headphone amplifier output ● Receiver amplifier output ● Built-in PLL and supporting clock input up to 27 MHz and TCXO (Temperature Compensated Crystal Oscillator) ● Power-down mode ● DSP parameter settings available for fine adjustment to acoustic characteristics of housing ● Provides a variety of middleware, drivers □ Power supply specification ● Core power supply ● Digital 3V-system power supply ● I/O power supply ● Analog circuit power supply ● Headphone amplifier power supply ● Receiver amplifier power supply DVDD D3VDD IOVDD1 to 3 AVDD HPVDD RCVDD 1.10V to 1.30V (Typ. 1.20V) 2.70V to 3.30V (Typ. 3.00V) 1.65V to 3.30V (Typ. 1.80V) 2.70V to 3.30V (Typ. 3.00V) 2.70V to 4.50V (Typ. 3.00V) 2.70V to 4.50V (Typ. 3.60V) □ Package ● Lead-free 77-ball FBGA package (YMU809-CZ) [Note] When using decode or encode function for compression audio, it needs to get each decoder or encoder license. 2 YMU809 „ SYSTEM CONFIGURATION EZAMPLES MC-3 can handle the voice processing concurrently with the audio CODEC processing available to improve the audio quality. Examples of the voice processing use are shown below. 1) PND with Hands-Free Capability 2) Mobile Phone for Voice Quality Improvement 3) Wi-Fi / Mobile Phone with Hands-Free Capability Noise Voice AGC NS AEC SRC ADC MIC Base band Voice or SRC NS AGC SSC Wi-Fi Audio Voice Improvement Digital or Analog I/F DAC Echo SP Amp. SP Receiver Amp. MC-3 Receiver ADC: A/D Converter, AEC: Acoustic Echo Canceller, AGC: Auto Gain Controller, DAC: D/A Converter, NS: Noise Suppressor, SRC: Sampling Rate Converter, SSC: Speech Speed Controller 3 YMU809 „ PIN CONFIGURATION FBGA 9X9 array with 77 balls 4 YMU809 „ Pin FUNCTIONS No. Pin Name I/O Power Supply G P I P G P P O P － － Function A1 A2 A3 A4 A5 A6 A7 A8 A9 DGND DVDD /CS IOVDD1 DGND IOVDD1 DVDD /IRQ IOVDD2 B1 B2 B3 B4 B5 PLLAGND A4 /WR D5 D6 G I I I/O I/O IOVDD1 IOVDD1 IOVDD1 IOVDD1 A power supply pin for PLL (A capacitor connection pin) CPU interface Address 4 CPU interface Write CPU interface Data Bus 5 CPU interface Data Bus 6 B6 B7 B8 B9 D7 SDOUT#1 SDOUT#0 DGND I/O O/Hi-Z O/Hi-Z G IOVDD1 IOVDD2 IOVDD2 － CPU interface Data Bus 7 Digital Audio #1 Data Output Digital Audio #0 Data Output A ground pin for digital circuits C1 C2 C3 C4 C5 C6 C7 C8 C9 PLLAVDD A3 /RD D2 D3 D4 LRCK#1 LRCK#0 DVDD P I I I/O I/O I/O I/O I/O P IOVDD1 IOVDD1 IOVDD1 IOVDD1 IOVDD1 IOVDD2 IOVDD2 － D1 D2 D3 D4 D5 D6 IOVDD3 A2 A1 D0 D1 GPIO P I I I/O I/O I/O IOVDD1 IOVDD1 IOVDD1 IOVDD1 IOVDD2 A power supply pin for CLKI CPU interface Address 2 CPU interface Address 1 CPU interface Data Bus 0 CPU interface Data Bus 1 GPIO control D7 D8 D9 BCLK#1 BCLK#0 IOVDD2 I/O I/O P IOVDD2 IOVDD2 － Digital Audio #1 Bit Clock Digital Audio #0 Bit Clock A power supply pin for pins except CPU I/F and CLKI E1 E2 E3 E6 E7 E8 E9 DVDD CLKI A0 TESTIO SDIN#1 SDIN#0 D3VDD P Is/Itcxo I I/O I I P － IOVDD1 － － － － IOVDD2 － － － － IOVDD3 IOVDD1 IOVDD2 IOVDD2 IOVDD2 － A ground pin for digital circuits A power supply pin for digital circuits CPU interface Chip Select A power supply pin for CPU interface pin A ground pin for digital circuits A power supply pin for CPU interface pin A power supply pin for digital circuits Interrupt output A power supply pin for pins except CPU I/F and CLKI A power supply pin for PLL CPU interface Address 3 CPU interface Read CPU interface Data Bus 2 CPU interface Data Bus 3 CPU interface Data Bus 4 Digital Audio #1 LR Clock Digital Audio #0 LR Clock A power supply pin for digital circuits A power supply pin for digital circuits Clock input CPU interface Address 0 I/O pin for test Digital Audio #1 Data Input Digital Audio #0 Data Input Digital power supply (3V system) PLLAGND pin connection Do not connect PLLAGND pin to the external ground. (It is connected to DGND internally.) 5 YMU809 No. F1 F2 F3 F6 Pin Name D3VDD DVDDC3 DGND DGND I/O P AI G G Power Supply － － － － F7 /TEST I IOVDD2 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 /RST HPVDD AVDD MIN1 MOUT1 MBS1 AUX1R AUX2R LINEOUTR HPOUTR HPGND AGND MIN2 Is AP AP AI AO AO AI AI AO AO AG AG AI IOVDD2 － － AVDD AVDD AVDD AVDD AVDD AVDD HPVDD － － AVDD H3 MIG2 AI AVDD H4 H5 H6 H7 H8 H9 MBS2 AUX1L AUX2L LINEOUTL HPOUTL RCOUT2 AO AI AI AO AO AO AVDD AVDD AVDD AVDD HPVDD RCVDD J1 VREF AI AVDD J2 HPC AI － J3 J4 J5 J6 J7 J8 J9 MIN3 MOUT3 MBS3 LINEOUTM RCVDD RCGND RCOUT1 AI AO AO AO AP AG AO AVDD AVDD AVDD AVDD － － RCVDD I/O symbol description AG Analog ground AI Analog input AO Analog output AP Analog power supply G Digital Ground I Digital input I/O Digital in/output Is Digital input (Schmitt) Itcxo Digital input (TCXO) O Digital output O/Hi-z Digital output (settable to Hi-z) P Digital power supply 6 Function Digital power supply (3V system) Capacitor connection pin of the digital-core power-supply division 3 A ground pin for digital circuits A ground pin for digital circuits A pin for test Be sure to connect to IOVDD2. Hardware reset input A power supply pin for headphone amplifier A power supply pin for analog circuits except amplifiers Microphone amplifier input #1 Microphone amplifier output #1 Microphone bias voltage #1 AUX#1 Rch input AUX#2 Rch input LINE output Rch Headphone amplifier Rch output A ground pin for headphone amplifier A ground pin for analog circuits except amplifiers Microphone amplifier input #2 Microphone 2 differential operation: Be sure to connect this pin to GND side of a microphone through a capacitor. Microphone 2 single-ended operation: Be sure to leave this pin open after the register setting (M2SNG=“1”). Microphone bias voltage #2 AUX#1 Lch input AUX#2 Lch input LINE output Lch Headphone amplifier Lch output Receiver amplifier differential output (-) Analog reference voltage Headphone output A capacitor is connected to this pin to prevent pop noise Microphone amplifier input #3 Microphone amplifier output #3 Microphone bias voltage #3 LINE output Mono A power supply pin for receiver amplifier A ground pin for receiver amplifier Receiver amplifier differential output (+) YMU809 „ BLOCK DIAGRAMS 〔1〕 Digital Block /RST 3D#0Send 3D#1Send /IRQ 3D#2Send Switch/Send/Panpot CHV OL2 VOV OL ③ (DIR#0) Clock Generation PLL CLKI 3D#3Send Lch Rch Sfx0Send Sfx1LSend Sfx1RSend BinauralLSend BinauralRSend GPIO GPIO 11ch 11ch ④ (DIR#1) 11ch ⑤ (ADC) 11ch ⑥ (C-DSP) (SPE & PM) Spectrum Analyzer ①-⑧ 8 to 1 SEL (E) Peak Meter Intermediate Register S P E_P M_S OURCE 出力FIFO (ENC_L) 入力FIFO EFIFO (6KB) SRC (ENC) Lch Rch Write-in FIFO 1 (ENC_ R) DFIFO _S OUR CE 0 SEL 1 DIT _S OUR CE_S E L "0" B DS P_S T B-DSP 2ch MUTE B DS P_A DOUT ③ (DIR#0) ⑦ Analog 1 AGC ⑤ (ADC) Parallel Conversion HPF 0 A D_DS P S E L (DIT#0) Level Determination DIT0_S RC_S OUR CE 2ch (L/Rch) 0 SRC ( DIR #1 ) DIR 1_FIFOW (DIT#1) DIT1_S RC_S OUR CE 9 to 1 SEL (A) DIT 1_S OUR CE "0" (R=R eserv ed) (DIT #1) 2 L/Rch ADC Range Determination ⑧ ① - ⑦ , R, ⑨ SRC ④ (DIR#1 ) ①-⑨ 2 ch (L/Rch) 0 Deemphasis Filter 9 to 1 SEL (C) 1 ② (SFX /Sound -Quality Improvement ) 1 SE L SDOUT#1 (DIT # 0) 2 SEL SDIN#1 SRC DIT0_S OUR CE Digital Audio I/F #1 BCLK#1 2 ch (L /Rch) 0 ⑨ SEL BYP ASS LRCK#1 ( DIR #0 ) DIR 0_FIFOW 1 ① B DS P_S T E NC _S RC_S OURC E_R Deemphasis Filter ① -⑨ SDOUT#0 SRC 9 to 1 SEL (B) SDIN#0 2ch (L/Rch) 0 SEL Digital Audio I/F #0 BCLK#0 SEL 1 LRCK#0 2 ch MUTE DFIFO (16KB) 1 1 4 t o 1 SEL (D) SEL SEL 0 10 band EQ 1 E NC _S RC_S OURC E_L 0 DIR_FIFOW _S E L 0 2ch FFIFO (1KB ) 2ch (C-DSP ) SE L FW Forward FIFO R E C_S TA RT (Path while B -DSP Is being stopped .) ⑥ 1 1ch D0-D7 1 SRC ( OUT) 14 to 1 SEL (D) A0-A4 RFIFO (6KB ) C-DSP /RD SEL /WR OFIFO (9KB) Read-out FIFO 0 ①L - ⑦L, ①R - ⑦R ①L - ⑦L, ①R - ⑦R CPU I/F （Interface Register） /CS Master Volume SWAP/ MONO DAC ATT HPF OVS P/S L/ Rch (Serial ) S/P DAC (DAC) DA C_S OURC E /TEST TESTIO Refer to the analog block diagram for details. 7 YMU809 The CPU interface is a 8-bit parallel interface. This is a register block which can be accessed through the Interface Register. There are registers for setting various functions in the Intermediate Register. FIFOs are prepared around C-DSP. The data can be written and read from the CPU I/F and the digital audio I/F. The FIFO size differs with each path. This is a block to mainly perform various decoding and encoding processes. The data can be inputted and outputted from the CPU I/F and the digital audio I/F via the FIFO. This is a programmable DSP that performs the sound-quality improvement such as 3D processing, effector processing, and compression processing. This is a 3-band + 7-band digital equalizer. The equalizer is prepared on the assumption that 3-band is used for a parametric equalizer and 7-band is for graphic equalizers. This is a digital audio input-output interface for two stereo lines. The two lines are independent from each other, and can be concurrently used. The interface supports data of 16/20/24 bit 2’s complement and a sampling frequency of 8 kHz to 48 kHz. In addition, it supports both master mode and slave mode. Various processing in B-DSP and C-DSP can be applied to the input audio data. The function to connect the two lines (bypass mode) is also prepared. Six SRCs are located on the input and output side of the digital audio path and C-DSP path. The SRC converts various sampling frequencies that were input from the digital audio interface into 48 kHz. And, other SRCs on the digital audio output side and the C-DSP input path converts data of a sampling frequency of 48 kHz into a sampling frequency of 8 kHz to 48 kHz. The SRC on the C-DSP output path is used for playback pitch control. GPIO can outputs a signal level of setting in the register, or can read an external pin status through a register. In addition, an interrupt also can be generated by detecting the change of input pin status. A clock of 10 MHz to 27 MHz can be input to CLKI pin. This section also supports “TCXO” mode, which accept a low amplitude input, as well as usual CMOS input. PLL part generates the clocks from an input clock through CLKI pin to use for internal of LSI. This is a block to process bit stream signals from A/D converter. The processing performed are Parallel conversion, Dither cut (High Pass Filter), AGC (Auto Gain Control), etc. 8 YMU809 〔2〕 Analog Block VOL2 spec. +22.5 to -22.5dB (1.5dB step) & MUTE MIXER ADL ADC Lch VOL2 To digital block ADC Rch VOL2 MIXER ADR DACL MOUT1 ATT MIXER STR ATT STL From digital block AUXR AUXL MIXER STL Microphone Input DAC Lch DACR DAC Rch STR ATT LINEOUTL MIXER LOL MIN1 Line Output VOL MIXER LOR + SEL MIG2 MOUT3 MIXER LOM ATT LINEOUTM MC3 MC2 MC1 DMC3 DMC2 DMC1 ATT2 spec. 0 to -46dB (1.0dB step) & MUTE SEL SEL Line Input AUX1L DAUXL VOL DIF_A1 + + SEL SEL AUX2R DAUXR VOL MIXER HPL ATT2 － ＋ HPOUTL MIXER HPR ATT2 － ＋ HPOUTR AUXL AUSEL MBS1 LINEOUTR VOL MIN3 AUX1R ATT ATT spec. 0 to -30dB (1.0dB step) & MUTE VOL AUX2L SEL MIN2 Headphone Amplifier AUXR τ HPC In VOL (or ATT, ATT2) surrounded by , there is the circuit for the noise reduction (zero cross detection) during the volume change. VOL spec. +12 to -33dB (1.5dB step) & MUTE MIXER RC ATT MBS3 RCOUT1 Microphone Bias Circuit RCOUT2 DACR DACL + STR STL AUXR AUXL MBS2 Receiver Amplifier + VREF VREF AVDD AGND HPVDD HPGND RCVDD RCGND 9 YMU809 3-channel microphone inputs are prepared. There is a volume circuit for each channel in the later stage. For microphone 2, differential/single-ended operation can be selected. Two stereo external analog inputs are prepared. And, for AUX1L/R, a differential input can be selected. There is a separate volume circuit for Lch and Rch in the later stage. A stereo A/D converter is used. The sampling frequency is 48 kHz and all the analog inputs can be converted into digital signals by mixing them. There is a volume circuit which is located on the previous stage of the A/D converter, and a volume for Lch and Rch can be separately controlled. This section converts 16-bit stereo data from the digital section (after the 4×oversampling processing) into analog signals. The sampling frequency is 192 kHz. This circuit controls whether to mix or mute signals from DAC or analog inputs. A mixer circuit is prepared for each output path. After mixing 3-channel microphone inputs and adjusting its volume, the circuit outputs it as side-tone to both the mixer for headphone amplifier and the mixer for receiver amplifier. One stereo and one mono line outputs are prepared. The circuit can mixes all the analog inputs and DAC outputs in each channel (Lch, Rch) separately and outputs it to the line-output. For stereo line, a differential output is selectable. A stereo headphone amplifier is mounted in the chip. This is a linear amplifier needing a DC-cut capacitor. The volume for the headphone path is specified as 0 dB to -46 dB and MUTE. Receiver amplifier with differential output is mounted in the chip. 10 YMU809 „ ELECTRICAL CHARACTERISTICS 〔1〕 Absolute Maximum Ratings Parameter DVDD pin, supply voltage IOVDD1 pin, supply voltage IOVDD2 pin, supply voltage IOVDD3 pin, supply voltage D3VDD pin, supply voltage AVDD pin, supply voltage HPVDD pin, supply voltage RCVDD pin, supply voltage Analog input voltage (*4) Digital input voltage 1 (*1) (*4) Digital input voltage 2 (*2) (*4) Digital input voltage 3 (*3) (*4) Power dissipation (*5) Storage temperature Symbol Min. Max. Unit DVDD IOVDD1 IOVDD2 IOVDD3 D3VDD AVDD HPVDD RCVDD VINA VIND1 VIND2 VIND3 Pd TSTG -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 1.70 4.20 4.20 4.20 4.20 4.20 5.20 5.20 AVDD+0.3 IOVDD1+0.3 IOVDD2+0.3 IOVDD3+0.3 1639 125 V V V V V V V V V V V V mW °C -50 Condition DGND, AGND, HPGND and RCGND are all 0V. (*1) Applicable pins are Input and input-output pins operated by IOVDD1. (*2) Applicable pins are Input and input-output pins operated by IOVDD2. (*3) Applicable pin is CLKI pin. (*4) The value is applied even when the supply voltage is out of the recommended operating voltage range. For example: An input voltage in excess of 0.3V becomes a violation when a voltage being input to a power supply pin is 0V (*5) Take this value as a reference because it is calculated by simulation based on a certain environment condition, Top= 25°C, mounted on a glass epoxy PCB (114.3 mm × 76.2 mm × 1.6 mm), and the board wiring density is 200%. When operating above Top= 25 °C, the value decreases 16.4 mW per 1 °C. 〔2〕 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit DVDD pin supply voltage IOVDD1 pin supply voltage DVDD IOVDD1 1.10 1.65 1.20 1.80 1.30 3.30 V V IOVDD2 pin, supply voltage IOVDD3 pin, supply voltage D3VDD pin, supply voltage (*1) AVDD pin, supply voltage (*1) HPVDD pin, supply voltage RCVDD pin, supply voltage Operating ambient temperature IOVDD2 IOVDD3 D3VDD AVDD HPVDD RGVDD TOP 1.65 1.65 2.70 2.70 2.70 2.70 -20 1.80 1.80 3.00 3.00 3.00 3.60 25 3.30 3.30 3.30 3.30 4.50 4.50 85 V V V V V V °C Condition DGND, AGND, HPGND and RCGND are all 0V. (*1) For D3VDD and AVDD, supply a same voltage from same regulator to keep D3VDD = AVDD. 11 YMU809 〔3〕 Current Consumption Parameter DVDD + PLLAVDD consumption current Conditions HE AAC decoder playback →DAC operation MP3 decoder playback →DAC operation DIR#0 → DAC operation IOVDD1 consumption current HE AAC decoder playback IOVDD2 consumption current DIR#0 → DIT#1 operation IOVDD3 consumption current (*8) Typ. (*1) Max. (*2) Unit 6.2 (*4) mA 5.3 (*5) mA 2.2 (*6) mA (*4) (*5) (*6) 0.1 mA 0.6 mA Normal operation (CMOS mode) 25 μA Normal operation (TCXO mode) 80 μA AVDD consumption current AP*= all “0” 15 mA D3VDD consumption current ADC, DAC operation 0.7 mA HPVDD consumption current (Headphone amplifier section) AP*= all “0”, no sound generated 1.1 mA At 16Ω load, f=1kHz, 1mW output (Lch/Rch simultaneously) AP*= all “0”, no sound generated 8.2 mA 1.1 mA At 32Ω load, f=1kHz, 10mW output 17.5 mA RCVDD consumption current (Receiver amplifier section) (*7) Power saving mode (*3) (*9) Total current of all power supplies 80 320 μA Power off mode (*3) Total current of all power supplies 2 20 μA (*1): Under the (Typ.) voltages of the Recommended Operating Conditions, ambient temperature is room temperature. (*2): Under the (Max.) voltages of the Recommended Operating Conditions, ambient temperature is room temperature. (*3): /CS input pin is fixed to VIH=IOVDD1, and other input pins are VIL=DGND, VIH= IOVDD1 and IOVDD2, IOVDD3. (*4): The value is at HE AAC data is during playback (fs=44.1 kHz, 48 kbps). Process of the B-DSP section is nothing. Digital blocks except DP0 to DP2, PLLRST* and CDSP_PS are power saving state. At PLL single mode (CLKI=18.432MHz). It increase +0.4mA when CLKI=19.2MHz. (*5): The value is at MP3 data is during playback (fs=44.1 kHz, 128 kbps). Process of the B-DSP section is nothing. Digital blocks except DP0 to DP2, PLLRST* and CDSP_PS are power saving state At PLL single mode (CLKI=18.432MHz). It increase +0.4mA when CLKI=19.2MHz. (*6): DA#0 settings are fs=44.1 kHz, BCLK=64fs and Master Mode. Process of the B-DSP section is nothing, Digital blocks except DP0 to DP2, PLLRST* and DA0_PS are power saving state. At PLL single mode (CLKI=18.432MHz). It increase +0.4mA when CLKI=19.2MHz. (*7): DA#0 and DA#1 settings are fs=48.0 kHz, BCLK=64fs and Master Mode. (*8): At CLKI=19.2 MHz (*9): *_PS= “1”, DP*= “1”, PLLRST*= “1”, ANA_RST= “1” 12 YMU809 〔4〕 DC Characteristics Parameter Symbol Input voltage “H” level 1 Input voltage “L” level 1 Input voltage “H” level 2 Input voltage “L” level 2 Input voltage “H” level 3 Input voltage “L” level 3 Input voltage “H” level 4 Input voltage “L” level 4 Output voltage “H” level 1 Output voltage “L” level 1 Output voltage “H” level 2 Output voltage “L” level 2 Schmitt width 1 Schmitt width 2 Input leakage current Input capacity VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL Vsh1 Vsh2 IL CI Condition (*1) (*1) (*2) (*2) (*3) (*3) /RST pin /RST pin (*1) IOH = (*4) (*1) IOL = (*4) (*2) IOH = (*4) (*2) IOL = (*4) /RST pin CLKI pin Min. Typ. Max. 0.70 × IOVDD1 0.30 × IOVDD1 0.70 × IOVDD2 0.30 × IOVDD2 0.75 × IOVDD3 0.25 × IOVDD3 0.75 × IOVDD2 0.25× IOVDD2 0.80 × IOVDD1 0.20 × IOVDD1 0.80 × IOVDD2 0.20 × IOVDD2 120 30 10 10 10 Unit V V V V V V V V V V V V mV mV μA pF Condition Under the Recommended Operating Conditions and Capacitor load=50pF. (*1) Applicable pins are operated by IOVDD1. (*2) Applicable pins are operated by IOVDD2. (*3) Applicable pin is CLKI (at CMOS mode). (*4) BCLK#0, BCLK#1 and GPIO are IOH = -2mA and IOL= +2mA. Other output pins are IOH = -1mA and IOL= +1mA. Notes Drive capability of output pins became larger as a voltage of IOVDD* is higher. Insert an adequate damping resistor according to use conditions. 13 YMU809 〔5〕 AC Characteristics (a) Power-on and Hardware-Reset Rules Parameter /RST “L” pulse width (*1) /RST (undefined → L) setup time (*2) Power supply rise time (*3) Power supply rise time interval (*4) Symbol Min. TRSTW TRSTS TVRISE TVSKW 1 0 Typ. 0 Max. Unit 10 50 μs μs ms ms Condition Under the Recommended Operating Conditions. (*1) This is the rule between /RST pin and last rising power supply of DVDD, IOVDD1 to 3 and D3VDD(=AVDD). HPVDD and RCVDD can be powered on even after /RST has been changed from “L” to “H”. (*2) This is a rule between IOVDD2 and /RST pin. (*3) This is the rule for power supply rise time. (This time is from power-on to reaching the minimum voltage of the recommended operating condition.) (*4) This is the rule for time interval difference between first rising and last rising power supplies among DVDD, IOVDD1 to 3 and D3VDD (=AVDD). TVRISE Power-on Start 2.7V D3VDD AVDD TVRISE Power-on Start 1.1V DVDD IOVDD1 IOVDD2 IOVDD3 TVRISE Power-on Start 1.65V 0.3V TVSKW TRSTS /RST TRSTW VIL= 0.25×IOVDD2 ↑ Be sure not to violate the Absolute Maximum Rating during the undefined period of /RST. Notes for the order of power supplies rising The power-on order between DVDD and IOVDD* is arbitrary; however, the following order is recommended. 1. Power-on IOVDD1 to IOVDD3 (The power-on order between IOVDD1 to IOVDD3 is arbitrary.) 2. Power-on DVDD 3. Power-on D3VDD (=AVDD) 4. Reset cancel (/RST= “H”) *) When DVDD is powered on earlier than IOVDD2, leak current same as power-save mode will flow to DVDD until IOVDD2 is up. 14 YMU809 Notes Be sure to input “L” to /RST pin at the same time as IOVDD2 rise. With the condition where IOVDD2 power supply is established and /RST pin is at L level, the circuit is configured so that input-output direction of pins operating at IOVDD2, and output level at the output pin are defined. The input-output direction of D0 to D7 pins is settled by the input polarity of /RD and /CS which operates at IOVDD1. Therefore, the input-output direction of D0 to D7 is settled even if IOVDD1 has already risen and DVDD is not yet. (Inputting “H” to /CS in conjunction with the rise of IOVDD1 is recommended). 15 YMU809 (b) Input Clock (CLKI) 1) CMOS Mode Parameter CLKI frequency CLKI rise / fall time CLKI High time CLKI Low time Allowable frequency deviation range Condition Symbol Min. 1 / Tfreq Trckc, Tfckc Th Tl － 10 Typ. 15 15 -100 Max. Unit 27 30 MHz ns ns ns ppm +100 Under the Recommended Operating Conditions 2) TCXO Mode Parameter CLKI frequency CLKI rise / fall time CLKI amplitude H (10MHz≤CLKI frequency≤27MHz) (*1) CLKI amplitude L (10MHz≤CLKI frequency≤27MHz) (*1) Wait time to stable operation (*1) Feedback resistance Allowable frequency deviation range Symbol Min. 1 / Tfreq Trckt, Tfckt Vmax – Vcenter 10 Typ. Max. Unit 0.30 27 50 0.35 × IOVDD3 MHz ns V Vcenter – Vmin 0.30 0.35 × IOVDD3 V Twait Rck - 2 13.5 -100 54 +100 ms kΩ ppm 27 Condition Under the Recommended Operating Conditions (*1) : The value is under the condition of which TCXO parts is AC-coupled with the CLKI pin with a capacitor of 1000pF. Be sure to use a capacitor of 1000pF for AC coupling. 16 YMU809 • The voltage level of which Duty of CLKI becomes 50% (High time = Low time) is defined as Vcenter. However, input of such waveform (Positive pulse, negative pulse, etc. with duty ratio logically out of shape) that cannot define the Vcenter shall be prohibited. • The measurement point of Trckt and Tfckt is defined by the time taken for variation between Vcenter + 0.30 [V] and Vcenter – 0.30 [V]. • The timing measurement level of Tfreq should be Vcenter (Duty=50% ). B Vcenter A OK : Input applicable to the definition of Vcenter [ Presence of a state of interval A = interval B ] B Vcenter A NO : Input not applicable to the definition of Vcenter [ Absence of a state of interval A = interval B ] Notes for the external circuit of CLKI pin Select TCXO mode or CMOS mode by CKSEL bit (A_ADR#5). Note that characteristics of CLKI pin's peripheral circuits and input signals vary depending on a setting value. Be sure to match the CKSEL setting value with characteristics of CLKI pin's external circuit and input signals. When used in TCXO mode : YMU809 1000pF CLKI A capacitor is required. Watch out for this input amplitude! Refer to “CLKI amplitude” of TCXO mode. Be sure to set the CKSEL to “1” When used in CMOS mode: YMU809 Capacitor connection (AC-coupling) is not required. CLKI Be sure to set the CKSEL to “0” 17 YMU809 (c) CPU Interface Timing The characteristics of the CPU interface are measured under the following conditions. VIL=0.20×IOVDD1 Input conditions in the measurement: VIH=0.80×IOVDD1, Measurement points: VIH=0.70×IOVDD1, VIL=0.30×IOVDD1 VOH=0.70 ×IOVDD1, VOL=0.30×IOVDD1 1) Write Cycle Parameter Address setup time Address hold time Chip select setup time Chip select hold time Write pulse width Data setup time Data hold time /CS, /WR, A0 to A4, D0 to D7 inputs raise/fall time Condition Symbol Min TADS TADH TCSS TCSH TWW TWDS TWDH TRFI 30 0 30 0 30 20 0 Max. Unit 20 ns ns ns ns ns ns ns ns Max. Unit Under the Recommended Operating Conditions 2) Read Cycle Parameter Address hold time Chip select hold time Access time from /RD pin Access time from /CS pin Access time from A0-A4 pin Data hold time from /RD pin High-impedance transition time from /RD pin /CS, /RD, A0 to A4 inputs raise/fall time Condition 18 Symbol Min TADH TCSH TACCRD TACCCS TACCAD TDHRD TDZRD TRFI 0 0 50 50 50 0 10 20 ns ns ns ns ns ns ns ns Under the Recommended Operating Conditions, Capacitor load=50pF, IOH and IOL = 0 mA. YMU809 3) Timing Chart in the Write Operation Notes : TADH : TCSH : TWDH : TADS : TCSS : The hold time of A0-A4 pin, which is defined with respect to the point where the rise of /WR has reached 0.70×IOVDD1 under the condition that both two specifications (TCSH , TWDH) are secured more than minimum value (=0ns). The hold time of /CS pin, which is defined with respect to the point where the rise of /WR has reached 0.70×IOVDD1 under the condition that both two specifications (TADH , TWDH) are secured more than minimum value (=0ns). The hold time of D0-D7 pins, which is defined with respect to the point where the rise of /WR has reached 0.70×IOVDD1 under the condition that both two specifications (TADH , TCSH) are secured more than minimum value (=0ns). The hold time of A0-A4 pin, which is defined with respect to the point where /WR has become invalid (0.30×IOVDD1) under the condition that all of three specifications (TCSS, TWW, TWDS) are secured more than minimum value. The hold time of /CS pin, which is defined with respect to the point where /WR has become invalid (0.30×IOVDD1) under the condition that all of three specifications (TADS, TWW, TWDS) are secured more than minimum value. 19 YMU809 4) Timing Chart in the Read Operation TRFI TRFI A0-A4 TACCAD TADH TRFI TCSH TRFI /CS TACCCS TRFI TRFI /RD TACCRD TDZRD TDHRD D0-D7 Valid Notes : TACCAD : The access time from when A0-A4 are defined (0.70×IOVDD1 or 0.30×IOVDD1) until when D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). /RD and /CS shall be defined beforehand (*1). TACCCS : The access time from when /CS is defined (0.30×IOVDD1) until when D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). A0-A4 and /RD shall be defined beforehand (*1). TACCRD : The access time from when /RD is defined (0.30×IOVDD1) until when D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). A0-A4 and /CS shall be defined beforehand (*1). TDHRD : It is the period of time when D0 to D7 keeps outputting (holding) valid data from the point of 0.30×IOVDD1 at which /RD changes its state from a valid level to an invalid level. Time more than 0ns shall be secured for TADH and TCSH. TDZRD : This indicates the period from when /RD becomes invalid (0.70×IOVDD1) until when D0-D7 becomes high impedance state under the condition that TADH and TCSH secures 0 ns or over. 20 YMU809 (*1) “defined beforehand”. Means: A0-A4: It indicates the state in which A0-A4 are defined (0.70×IOVDD1 or 0.30×IOVDD1) more than TACCAD before when the reference is placed on a point where D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). /CS: It indicates the state in which /CS is defined (0.30×IOVDD1) more than TACCCS before when the reference is placed on a point where D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). /RD: It indicates the state in which /RD is defined (0.30×IOVDD1) more than TACCRD before when the reference is placed on a point where D0-D7 are defined (0.70×IOVDD1 or 0.30×IOVDD1). 21 YMU809 5) Waiting time during access Parameter Symbol Min 70 30 90 60 100 90 40 Write – Write access waiting time (*1) TWAITWW Read – Read access waiting time (*2) TWAITRR Write – Read access waiting time (*3) TWAITWR Read – Write access waiting time TWAITRW Max. Unit ns ns ns ns (*1): It depends on the accessing area. See the table on the next page. (*2): TWAITRR of REC_FIFO continuous read is 90ns (*4). The rest of it is 60ns. (*3): TWAITWR of DEC_FIFO (Write) – DFIFO_FLG (Read) and FSQ_FIFO (Write) – FFIFO_FLG (Read) is 100ns (*5). The rest of it is 90ns. (*4): It is the value when CDSP_CLK_FREQ_HOST (DEC_B_ADR#111) is set to “3” (73.728MHz). When CDSP_CLK_FREQ_HOST to “1” (36.864MHz), it is 180ns. (*5): It is the value when CDSP_CLK_FREQ_HOST (DEC_B_ADR#111) is set to “3” (73.728MHz). When CDSP_CLK_FREQ_HOST to “1” (36.864MHz), it is 200ns. /WR VIH TWAITWW /RD VIH TWAITRR /WR VIH VIH TWAITWR /RD 22 TWAITRW VIH YMU809 i) Waiting Time for Write – Write The table below shows the write waiting time (TWAITWW) when writing into the same address (A_ADR#) continuously. Note that the waiting time varies depending on address values. A_ADR# Register name Write waiting time (Min.) #0 EIRQ, BANK 30ns Supplementary (when writing into the same A_ADR# continuously) #1 B_ADR 30ns #2 W_WINDOW — (Accessed together with #1) #3 RST1 — (In actual use, no chance of continuous write) #4 RST3, RWSW3 30ns (*1) #5 CKSEL, PLLRST*, DP* 30ns (*1) #6 DA*_INV, DA*_MS, DA*_MASK 30ns #7 DA_BYPASS, DA*_*HIZ 30ns #8 GP_DR, GP_MASK, GP_DDR, GP_MODE 30ns #10 ANA_RST — (In actual use, no chance of continuous write) #16 DEC_B_ADR 30ns #17 DEC_W_WINDOW — (Accessed together with #16) #18 DEC_FIFO 70ns #19 FSQ_FIFO 70ns #20 Interrupt flag (C-DSP related) 70ns #21 Interrupt flag enable (C-DSP related) 70ns #22 Interrupt flag 70ns #23 Interrupt flag enable 70ns #24 ANA_WADR 70ns #25 ANA_WDATA 70ns #26 ANA_RADR — (In actual use, no chance of continuous write) #27 AVALID — (In actual use, no chance of continuous write) #28 *_PS 30ns (*1), (*2) (*1): Set them according to the initialization procedure. (*2): For *_PS bits except CDSP_PS, it takes time up to 1/fs_SY to reflect the setting after writing. Supplementary Explanation ▪ When writing to other than above address (A_ADR#), waiting time is 70ns minimum. 23 YMU809 ii) Waiting Time for Read – Read The table below shows the waiting time (TWAITRR) for Read-Read operations when reading from the same address (A_ADR#) continuously. A_ADR# Register name Read waiting time (Min.) Supplementary (when reading from the same A_ADR# continuously) #0 EIRQ, BANK, BUSY, IRQ #1 B_ADR 60ns 60ns #2 R_WINDOW — (Accessed together with #1) #3 RST1 60ns #4 RST3, RWSW3, PWSW3FLG 60ns #5 CKSEL, PLLRST*, DP* 60ns #6 DA*_INV, DA*_MS, DA*_MASK 60ns #7 DA_BYPASS, DA*_*HIZ 60ns #8 GP_DR, GP_MASK, GP_DDR, GP_MODE 60ns #10 ANA_RST 60ns #15 HW_ID 60ns #16 DEC_B_ADR 60ns #17 DEC_W_WINDOW — (Accessed together with #16) #18 REC_FIFO 90ns #20 Interrupt flag (C-DSP related) 60ns #21 Interrupt flag enable (C-DSP related) 60ns #22 Interrupt flag 60ns #23 Interrupt flag enable 60ns #24 ANA_WADR — (Normally, no chance of continuous read) #25 ANA_WDATA — (Normally, no chance of continuous read) #26 ANA_RADR — (Normally, no chance of continuous read) #27 AVALID 60ns #28 *_PS 60ns (*1): It is the value when CDSP_CLK_FREQ_HOST (DEC_B_ADR#111) is set to “3” (73.728MHz). When CDSP_CLK_FREQ_HOST to “1” (36.864MHz), it is 180ns. Supplementary Explanation * When reading to other than above address (A_ADR#), waiting time is 60ns minimum. In actual use, continuous read address is REC_FIFO(A_ADR#18) only. 24 (*1) YMU809 (d) Digital Audio Interface Timing The characteristics are measured under the following conditions. Input conditions in the measurement: VIH=0.80×IOVDD2, Measurement points: VIH=0.70×IOVDD2, VOH=0.70×IOVDD2, VIL=0.20×IOVDD2 VIL=0.30×IOVDD2 VOL=0.30×IOVDD2 The following specifications are common to bath DA#0 and DA#1 systems. 1) Master Mode Parameter BCLK#* output frequency (*2)(*3) BCLK#* output “H” time BCLK#* output “L” time LRCK#* output frequency (*3) SDIN#* inputs raise/fall time Symbol Min. 1 / TBCLKW TBCLKHW TBCLKLW Typ. Max. 64fs_DA 48fs_DA 32fs_DA (*1) kHz 120 120 1 / TLRCKW Unit ns ns fs_DA(*1) TRFI kHz 20 ns Condition Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA (*1) fs_DA is a sampling frequency of the digital audio interface. (*2) BCLK#0 and #1 outputs have logical jitters. (*3) The frequency may move over a little from the ideal value depending on CLKI frequency and PLL setting. Parameter Symbol Min. TLRCKD_A TSDIS_A -20 65 SDIN#* inputs hold time TSDIH_A 65 SDOUT#* output delay time TSDOD_A 30 LRCK#* output delay time SDIN#* inputs setup time Condition Typ. Max. Unit +20 ns ns 105 ns ns Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA Parameter Symbol Min. TLRCKD_B TSDIS_B -20 65 SDIN#* inputs hold time TSDIH_B 65 SDOUT#* output delay time TSDOD_B 30 LRCK#* output delay time SDIN#* inputs setup time Condition Typ. Max. Unit +20 ns ns 105 ns ns Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA 25 YMU809 The timing charts of DA#0 side are shown here. The charts of DA#1 side are the same. TBCLKW TBCLKHW TBCLKLW TRFO BCLK#0 (Output) TRFO 0.70×IOVDD2 0.50×IOVDD2 0.30×IOVDD2 TLRCKW LRCK#0 (Output) 0.50×IOVDD2 TRFI SDIN#0 (Input) 26 TRFI 0.70×IOVDD2 0.30×IOVDD2 YMU809 27 YMU809 2) Slave Mode Parameter Symbol BCLK#* inputs frequency 1 / TBCLKW BCLK#* inputs “H” time BCLK#* inputs “L” time LRCK#* output frequency BCLK#* LRCK#*, SDIN#* inputs raise/fall time TBCLKHW TBCLKLW 1 / TLRCKW TRFI Min. Typ. Max. 64fs_DA 48fs_DA 32fs_DA (*1) Unit kHz 120 120 fs_DA(*1) 20 ns ns kHz ns Condition Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA (*1) fs_DA is a sampling frequency of the digital audio interface. Allowable Input Frequency (LRCK#0, #1) Range In the slave mode, the allowable range of input frequency (LRCK#0, #1) is predetermined. Normal playback operation cannot be guaranteed when a frequency is not within the range. Parameter Symbol Min. LRCK#* inputs setup time LRCK #* inputs hold time TLRCKS_A TLRCKH_A 65 65 ns ns SDIN#* inputs setup time TSDIS_A 65 ns SDIN#* inputs hold time TSDIH_A 65 SDOUT#* output delay time TSDOD_A 55 Condition Typ. Max. Unit ns 135 ns Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA Parameter LRCK#* inputs setup time LRCK #* inputs hold time Min. TLRCKS_B TLRCKH_B 65 65 Typ. Max. Unit ns ns SDIN#* inputs setup time TSDIS_B 65 ns SDIN#* inputs hold time TSDIH_B 65 ns SDOUT#* output delay time TSDOD_B 55 Condition 28 Symbol 135 Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA ns YMU809 The timing charts of DA#0 side are shown here. The charts of DA#1 side are the same. TBCLKW TBCLKHW TBCLKLW TRFI BCLK#0 (Input) TRFI 0.70×IOVDD2 0.50×IOVDD2 0.30×IOVDD2 TLRCKW TRFI TRFI LRCK#0 (Input) 0.70×IOVDD2 0.50×IOVDD2 0.30×IOVDD2 TRFI SDIN#0 (Input) TRFI 0.70×IOVDD2 0.30×IOVDD2 29 YMU809 30 YMU809 3) Bypass Mode Parameter SDIN#* → SDOUT#* delay time (*1) BCLK#* → BCLK#* delay time (*2) LRCK#* → LRCK#* delay time (*3) Symbol TDBYPSD TDBYPSB TDBYPSL Min. Typ. Max. Unit 50 50 50 ns ns ns Condition Under the Recommended Operating Conditions, Capacitor load=30pF, IOH and IOL= 0mA (*1) Applicable path: SDIN#0 → SDOUT#1, SDIN#1 → SDOUT#0 (*2) Applicable path: BCLK#0 (input) → BCLK#1 (output), BCLK#1 (input) → BCLK#0 (output) (*3) Applicable path: LRCK#0 (input) → LRCK#1 (output), LRCK#1 (input) → LRCK#0 (output) 31 YMU809 (e) Other Digital Input Pin (GPIO) Parameter Input raise/fall time Condition 32 Symbol TRFI Under the Recommended Operating Conditions Min. Typ. Max. Unit 20 ns YMU809 〔6〕 Analog Characteristics The measurement conditions are as follows. TOP=25°C DVDD=1.20V, IOVDD1=IOVDD2=IOVDD3=1.80V, AVDD=D3VDD==3.00V, HPVDD=3.00V RCVDD=3.60V (a) Headphone Amplifier Parameter Min. GAIN setting (fixed) Minimum load resistance (RL) Maximum output voltage amplitude (RL=16Ω) Maximum output power (RL=16Ω, THD+N≤1.0%) THD + N (RL=16Ω, f=1kHz, 5mW output) Noise in no signal (A-filter: weighting filter) PSRR (f=1kHz) Typ. Max. 1 16 1.5 18 0.03 -105 77 Unit Times Ω Vp-p mW % dBV dB (b) Receiver Amplifier Parameter Min. Gain setting (fixed) Minimum load resistance (RL) Maximum output voltage amplitude (RL=32Ω) Maximum output power (RL=32Ω, THD+N≤1.0%) THD+N (RL=32Ω, f= 1kHz) Noise in no signal (A-filter) PSRR Amplitude center potential Differential output voltage Typ. Max. ±1 32 3.8 55 0.025 -100 90 0.5×AVDD 3 Unit Times Ω Vp-p mW % dBV dB V mV (c) MIC Amplifier #1, #3 Parameter Gain settable range Maximum output voltage amplitude THD+N (f= 1kHz, at 20dB Gain) (*) Noise in no signal (A-filter, at 20dB Gain) (*) Input impedance Feedback resistance between MIN1 and MOUT1 (MIN3 and MOUT3) Min. Typ. 2.7 0.005 -92 10 20 Max. Unit 30 dB Vp-p % dBV MΩ kΩ (*) It is measured at MOUT1, MOUT3. 33 YMU809 (d) MIC Amplifier #2 (Single-ended/Differential) Parameter Min. Gain settable range Gain step width THD+N (f= 1kHz, at 20dB Gain, Single-ended) (*) THD+N (f= 1kHz,at 20dB Gain, Differential) (*) Noise in no signal (A-filter, at 20dB Gain, Single-ended) (*) Noise in no signal (A-filter, at 20dB Gain, Differential) (*) Input impedance (at +15dB Gain) Input impedance (at +20dB Gain) Input impedance (at +25dB Gain) Input impedance (at +30dB Gain) +15 Typ. Max. Unit +30 dB dB % % dBV dBV kΩ kΩ kΩ kΩ Max. Unit 2.0 V mA dBV Max. Unit 5 0.009 0.011 -88 -86 61.6 37.1 21.7 12.5 (*) It is measured at LINEOUTL pin. (MC*VOL and LOVOL_L are set to 0dB.) (e) MIC Bias #1 to #3 Parameter Min. Output voltage Output current Noise level (A-filter) Typ. 2.0 -108 (f) VREF Parameter Min. VREF voltage Typ. 0.5×AVDD V (g) DAC Parameter Resolution Full scale output voltage THD+N (f= 1 kHz) Noise in no signal (A-filter) Pass frequency band Min. Typ. Max. Unit 0.46×fs_SY Bit Vp-p % dBV Hz Max. Unit 0.4×fs_SY Bit Vp-p % dBFS Hz Max. Unit 0 dB dB dB 16 2.0 0.04 -100 20 (*) (*) when setting the high-pass filter of the DAC path to the default value. (h) ADC Parameter Resolution Maximum input voltage (-3dBFS) THD+N (f= 1kHz) Noise in no signal (A-filter) Pass frequency band Min. Typ. 16 2.0 0.015 -94 20 (*) (*) when setting the high-pass filter of the ADC path to the default value. (i) Headphone Volume (HPVOL_[L/R]) Parameter Volume setting range Volume step width MUTE attenuation rate 34 Min. Typ. -46 1 80 YMU809 (j) LINEOUT Volume (LOVOL_[L/R/M]) Parameter Min. Volume setting range Volume step width Attenuation rate at the time of Mute Minimum load resistance Maximum output voltage amplitude Output impedance -30 Typ. Max. Unit 0 10 2.7 300 600 dB dB dB kΩ Vp-p Ω Typ. Max. Unit +22.5 dB dB dB Max. Unit +12 dB dB dB Max. Unit +12 dB dB dB kΩ kΩ Max. Unit 0 dB dB dB Max. Unit 0 dB dB dB 1 80 (k) ADC Volume (ADVOL_[L/R]) Parameter Volume setting range Volume step width MUTE attenuation rate Min. -22.5 1.5 80 (l) MIC#1 to #3 Volume (MC[1/2/3]VOL) Parameter Volume setting range Volume step width MUTE attenuation rate Min. Typ. -33 1.5 80 (m) AUX Volume (AUVOL_[L/R]) Parameter Volume setting range Volume step width MUTE attenuation rate Input impedance Input impedance (AUX1L /1R in differential input) Min. Typ. -33 1.5 80 60 120 (n) Side Tone Volume (STVOL_[L/R]) Parameter Volume setting range Volume step width MUTE attenuation rate Min. Typ. -30 1.0 80 (o) Receiver Volume (RCVOL) Parameter Volume setting range Volume step width MUTE attenuation rate Min. Typ. -30 1 80 35 YMU809 „ PACKAGE DIMENSIONS 36 YMU809 „ PRECAUTIONS AND INSTRUCTIONS FOR SAFETY 37 YMU809 „ IMPORTANT NOTICE